PANDN (XMM, M128) - Port Usage

With blocking instructions for port '2':

Code:

   0:	66 45 8b 46 40       	mov    r8w,WORD PTR [r14+0x40]
   5:	66 45 8b 4e 42       	mov    r9w,WORD PTR [r14+0x42]
   a:	66 45 8b 56 44       	mov    r10w,WORD PTR [r14+0x44]
   f:	66 45 8b 5e 46       	mov    r11w,WORD PTR [r14+0x46]
  14:	66 45 8b 66 48       	mov    r12w,WORD PTR [r14+0x48]
  19:	66 41 8b 5e 4a       	mov    bx,WORD PTR [r14+0x4a]
  1e:	66 41 8b 4e 4c       	mov    cx,WORD PTR [r14+0x4c]
  23:	66 41 8b 56 4e       	mov    dx,WORD PTR [r14+0x4e]
  28:	66 45 8b 46 40       	mov    r8w,WORD PTR [r14+0x40]
  2d:	66 45 8b 4e 42       	mov    r9w,WORD PTR [r14+0x42]
  32:	66 41 0f df 06       	pandn  xmm0,XMMWORD PTR [r14]

Init:
```
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.01
- Reference cycles: 11.05
- UOPS_PORT_2: 11.0

⇨ One μop that can only use port '2'

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	66 0f 55 ca          	andnpd xmm1,xmm2
   4:	66 0f 55 da          	andnpd xmm3,xmm2
   8:	66 0f 55 e2          	andnpd xmm4,xmm2
   c:	66 0f 55 ea          	andnpd xmm5,xmm2
  10:	66 0f 55 f2          	andnpd xmm6,xmm2
  14:	66 0f 55 fa          	andnpd xmm7,xmm2
  18:	66 44 0f 55 c2       	andnpd xmm8,xmm2
  1d:	66 44 0f 55 ca       	andnpd xmm9,xmm2
  22:	66 44 0f 55 d2       	andnpd xmm10,xmm2
  27:	66 44 0f 55 da       	andnpd xmm11,xmm2
  2c:	66 41 0f df 06       	pandn  xmm0,XMMWORD PTR [r14]

Init:

PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
PXOR XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.01
- Reference cycles: 11.01
- UOPS_PORT_0: 3.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_5: 4.0

⇨ One μop that can only use ports {'0', '1', '5'}

With an indexed addressing mode

With blocking instructions for port '2':

Code:

   0:	66 45 8b 46 40       	mov    r8w,WORD PTR [r14+0x40]
   5:	66 45 8b 4e 42       	mov    r9w,WORD PTR [r14+0x42]
   a:	66 45 8b 56 44       	mov    r10w,WORD PTR [r14+0x44]
   f:	66 45 8b 5e 46       	mov    r11w,WORD PTR [r14+0x46]
  14:	66 45 8b 66 48       	mov    r12w,WORD PTR [r14+0x48]
  19:	66 41 8b 5e 4a       	mov    bx,WORD PTR [r14+0x4a]
  1e:	66 41 8b 4e 4c       	mov    cx,WORD PTR [r14+0x4c]
  23:	66 41 8b 56 4e       	mov    dx,WORD PTR [r14+0x4e]
  28:	66 45 8b 46 40       	mov    r8w,WORD PTR [r14+0x40]
  2d:	66 45 8b 4e 42       	mov    r9w,WORD PTR [r14+0x42]
  32:	66 43 0f df 04 2e    	pandn  xmm0,XMMWORD PTR [r14+r13*1]

Init:
```
PXOR XMM0, XMM0;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.01
- Reference cycles: 11.04
- UOPS_PORT_2: 11.0

⇨ One μop that can only use port '2'

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	66 0f 55 ca          	andnpd xmm1,xmm2
   4:	66 0f 55 da          	andnpd xmm3,xmm2
   8:	66 0f 55 e2          	andnpd xmm4,xmm2
   c:	66 0f 55 ea          	andnpd xmm5,xmm2
  10:	66 0f 55 f2          	andnpd xmm6,xmm2
  14:	66 0f 55 fa          	andnpd xmm7,xmm2
  18:	66 44 0f 55 c2       	andnpd xmm8,xmm2
  1d:	66 44 0f 55 ca       	andnpd xmm9,xmm2
  22:	66 44 0f 55 d2       	andnpd xmm10,xmm2
  27:	66 44 0f 55 da       	andnpd xmm11,xmm2
  2c:	66 43 0f df 04 2e    	pandn  xmm0,XMMWORD PTR [r14+r13*1]

Init:

PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
PXOR XMM0, XMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.01
- Reference cycles: 11.01
- UOPS_PORT_0: 3.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_5: 4.0

⇨ One μop that can only use ports {'0', '1', '5'}