MOVSXD (R64, M32) - Port Usage

With blocking instructions for port '2':

Code:

   0:	66 45 8b 4e 40       	mov    r9w,WORD PTR [r14+0x40]
   5:	66 45 8b 56 42       	mov    r10w,WORD PTR [r14+0x42]
   a:	66 45 8b 5e 44       	mov    r11w,WORD PTR [r14+0x44]
   f:	66 45 8b 66 46       	mov    r12w,WORD PTR [r14+0x46]
  14:	66 41 8b 5e 48       	mov    bx,WORD PTR [r14+0x48]
  19:	66 41 8b 4e 4a       	mov    cx,WORD PTR [r14+0x4a]
  1e:	66 41 8b 56 4c       	mov    dx,WORD PTR [r14+0x4c]
  23:	66 45 8b 4e 40       	mov    r9w,WORD PTR [r14+0x40]
  28:	66 45 8b 56 42       	mov    r10w,WORD PTR [r14+0x42]
  2d:	66 45 8b 5e 44       	mov    r11w,WORD PTR [r14+0x44]
  32:	4d 63 06             	movsxd r8,DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.01
- Reference cycles: 11.0
- UOPS_PORT_2: 11.0

⇨ One μop that can only use port '2'

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	4d 63 06             	movsxd r8,DWORD PTR [r14]

Init:

PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.01
- Reference cycles: 11.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_5: 3.0

⇨ One μop that can only use ports {'0', '1', '5'}

With an indexed addressing mode

With blocking instructions for port '2':

Code:

   0:	66 45 8b 4e 40       	mov    r9w,WORD PTR [r14+0x40]
   5:	66 45 8b 56 42       	mov    r10w,WORD PTR [r14+0x42]
   a:	66 45 8b 5e 44       	mov    r11w,WORD PTR [r14+0x44]
   f:	66 45 8b 66 46       	mov    r12w,WORD PTR [r14+0x46]
  14:	66 41 8b 5e 48       	mov    bx,WORD PTR [r14+0x48]
  19:	66 41 8b 4e 4a       	mov    cx,WORD PTR [r14+0x4a]
  1e:	66 41 8b 56 4c       	mov    dx,WORD PTR [r14+0x4c]
  23:	66 45 8b 4e 40       	mov    r9w,WORD PTR [r14+0x40]
  28:	66 45 8b 56 42       	mov    r10w,WORD PTR [r14+0x42]
  2d:	66 45 8b 5e 44       	mov    r11w,WORD PTR [r14+0x44]
  32:	4f 63 04 2e          	movsxd r8,DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.01
- Reference cycles: 11.04
- UOPS_PORT_2: 11.0

⇨ One μop that can only use port '2'

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	4f 63 04 2e          	movsxd r8,DWORD PTR [r14+r13*1]

Init:

PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.01
- Reference cycles: 11.01
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_5: 3.0

⇨ One μop that can only use ports {'0', '1', '5'}