INC_LOCK (M32) - Port Usage

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	0f 7e c2             	movd   edx,mm0
  1d:	41 0f 7e c0          	movd   r8d,mm0
  21:	41 0f 7e c1          	movd   r9d,mm0
  25:	41 0f 7e c2          	movd   r10d,mm0
  29:	41 0f 7e c3          	movd   r11d,mm0
  2d:	41 0f 7e c4          	movd   r12d,mm0
  31:	0f 7e c3             	movd   ebx,mm0
  34:	0f 7e c1             	movd   ecx,mm0
  37:	0f 7e c2             	movd   edx,mm0
  3a:	41 0f 7e c0          	movd   r8d,mm0
  3e:	41 0f 7e c1          	movd   r9d,mm0
  42:	41 0f 7e c2          	movd   r10d,mm0
  46:	41 0f 7e c3          	movd   r11d,mm0
  4a:	41 0f 7e c4          	movd   r12d,mm0
  4e:	0f 7e c3             	movd   ebx,mm0
  51:	0f 7e c1             	movd   ecx,mm0
  54:	0f 7e c2             	movd   edx,mm0
  57:	41 0f 7e c0          	movd   r8d,mm0
  5b:	41 0f 7e c1          	movd   r9d,mm0
  5f:	41 0f 7e c2          	movd   r10d,mm0
  63:	41 0f 7e c3          	movd   r11d,mm0
  67:	41 0f 7e c4          	movd   r12d,mm0
  6b:	0f 7e c3             	movd   ebx,mm0
  6e:	0f 7e c1             	movd   ecx,mm0
  71:	0f 7e c2             	movd   edx,mm0
  74:	41 0f 7e c0          	movd   r8d,mm0
  78:	41 0f 7e c1          	movd   r9d,mm0
  7c:	41 0f 7e c2          	movd   r10d,mm0
  80:	41 0f 7e c3          	movd   r11d,mm0
  84:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Init:
```
PXOR MM0, MM0
```
Show nanoBench command
Results:
- Instructions retired: 37.0
- Core cycles: 36.85
- Reference cycles: 26.12
- UOPS_PORT_0: 36.0

With blocking instructions for port '1':

Code:

   0:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
   7:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
   e:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  15:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  1c:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  23:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  2a:	66 f2 41 0f 38 f1 d1 	crc32  edx,r9w
  31:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  38:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  3f:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  46:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  4d:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  54:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  5b:	66 f2 41 0f 38 f1 d1 	crc32  edx,r9w
  62:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  69:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  70:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  77:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  7e:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  85:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  8c:	66 f2 41 0f 38 f1 d1 	crc32  edx,r9w
  93:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  9a:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  a1:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  a8:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  af:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  b6:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  bd:	66 f2 41 0f 38 f1 d1 	crc32  edx,r9w
  c4:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  cb:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  d2:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  d9:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  e0:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  e7:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  ee:	66 f2 41 0f 38 f1 d1 	crc32  edx,r9w
  f5:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  fc:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 37.0
- Core cycles: 36.81
- Reference cycles: 25.56
- UOPS_PORT_1: 36.0

With blocking instructions for port '4':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  35:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  3c:	4d 89 86 a0 00 00 00 	mov    QWORD PTR [r14+0xa0],r8
  43:	4d 89 86 a8 00 00 00 	mov    QWORD PTR [r14+0xa8],r8
  4a:	4d 89 86 b0 00 00 00 	mov    QWORD PTR [r14+0xb0],r8
  51:	4d 89 86 b8 00 00 00 	mov    QWORD PTR [r14+0xb8],r8
  58:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
  5c:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
  60:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
  64:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  68:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  6c:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  70:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  74:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  78:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  7f:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  86:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  8d:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  94:	4d 89 86 a0 00 00 00 	mov    QWORD PTR [r14+0xa0],r8
  9b:	4d 89 86 a8 00 00 00 	mov    QWORD PTR [r14+0xa8],r8
  a2:	4d 89 86 b0 00 00 00 	mov    QWORD PTR [r14+0xb0],r8
  a9:	4d 89 86 b8 00 00 00 	mov    QWORD PTR [r14+0xb8],r8
  b0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
  b4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
  b8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
  bc:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  c0:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 37.0
- Core cycles: 54.48
- Reference cycles: 39.19
- UOPS_PORT_4: 40.61

⇨ One μop that can only use port '4'

With blocking instructions for port '5':

Code:

   0:	66 0f 3a 21 c1 02    	insertps xmm0,xmm1,0x2
   6:	66 0f 3a 21 d1 02    	insertps xmm2,xmm1,0x2
   c:	66 0f 3a 21 d9 02    	insertps xmm3,xmm1,0x2
  12:	66 0f 3a 21 e1 02    	insertps xmm4,xmm1,0x2
  18:	66 0f 3a 21 e9 02    	insertps xmm5,xmm1,0x2
  1e:	66 0f 3a 21 f1 02    	insertps xmm6,xmm1,0x2
  24:	66 0f 3a 21 f9 02    	insertps xmm7,xmm1,0x2
  2a:	66 44 0f 3a 21 c1 02 	insertps xmm8,xmm1,0x2
  31:	66 44 0f 3a 21 c9 02 	insertps xmm9,xmm1,0x2
  38:	66 44 0f 3a 21 d1 02 	insertps xmm10,xmm1,0x2
  3f:	66 44 0f 3a 21 d9 02 	insertps xmm11,xmm1,0x2
  46:	66 44 0f 3a 21 e1 02 	insertps xmm12,xmm1,0x2
  4d:	66 0f 3a 21 c1 02    	insertps xmm0,xmm1,0x2
  53:	66 0f 3a 21 d1 02    	insertps xmm2,xmm1,0x2
  59:	66 0f 3a 21 d9 02    	insertps xmm3,xmm1,0x2
  5f:	66 0f 3a 21 e1 02    	insertps xmm4,xmm1,0x2
  65:	66 0f 3a 21 e9 02    	insertps xmm5,xmm1,0x2
  6b:	66 0f 3a 21 f1 02    	insertps xmm6,xmm1,0x2
  71:	66 0f 3a 21 f9 02    	insertps xmm7,xmm1,0x2
  77:	66 44 0f 3a 21 c1 02 	insertps xmm8,xmm1,0x2
  7e:	66 44 0f 3a 21 c9 02 	insertps xmm9,xmm1,0x2
  85:	66 44 0f 3a 21 d1 02 	insertps xmm10,xmm1,0x2
  8c:	66 44 0f 3a 21 d9 02 	insertps xmm11,xmm1,0x2
  93:	66 44 0f 3a 21 e1 02 	insertps xmm12,xmm1,0x2
  9a:	66 0f 3a 21 c1 02    	insertps xmm0,xmm1,0x2
  a0:	66 0f 3a 21 d1 02    	insertps xmm2,xmm1,0x2
  a6:	66 0f 3a 21 d9 02    	insertps xmm3,xmm1,0x2
  ac:	66 0f 3a 21 e1 02    	insertps xmm4,xmm1,0x2
  b2:	66 0f 3a 21 e9 02    	insertps xmm5,xmm1,0x2
  b8:	66 0f 3a 21 f1 02    	insertps xmm6,xmm1,0x2
  be:	66 0f 3a 21 f9 02    	insertps xmm7,xmm1,0x2
  c4:	66 44 0f 3a 21 c1 02 	insertps xmm8,xmm1,0x2
  cb:	66 44 0f 3a 21 c9 02 	insertps xmm9,xmm1,0x2
  d2:	66 44 0f 3a 21 d1 02 	insertps xmm10,xmm1,0x2
  d9:	66 44 0f 3a 21 d9 02 	insertps xmm11,xmm1,0x2
  e0:	66 44 0f 3a 21 e1 02 	insertps xmm12,xmm1,0x2
  e7:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 37.0
- Core cycles: 36.81
- Reference cycles: 24.99
- UOPS_PORT_5: 35.96

With blocking instructions for ports {'0', '1'}:

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  30:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  35:	66 0f 58 c1          	addpd  xmm0,xmm1
  39:	66 0f 58 d1          	addpd  xmm2,xmm1
  3d:	66 0f 58 d9          	addpd  xmm3,xmm1
  41:	66 0f 58 e1          	addpd  xmm4,xmm1
  45:	66 0f 58 e9          	addpd  xmm5,xmm1
  49:	66 0f 58 f1          	addpd  xmm6,xmm1
  4d:	66 0f 58 f9          	addpd  xmm7,xmm1
  51:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  56:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  5b:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  60:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  65:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  6a:	66 0f 58 c1          	addpd  xmm0,xmm1
  6e:	66 0f 58 d1          	addpd  xmm2,xmm1
  72:	66 0f 58 d9          	addpd  xmm3,xmm1
  76:	66 0f 58 e1          	addpd  xmm4,xmm1
  7a:	66 0f 58 e9          	addpd  xmm5,xmm1
  7e:	66 0f 58 f1          	addpd  xmm6,xmm1
  82:	66 0f 58 f9          	addpd  xmm7,xmm1
  86:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  8b:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  90:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  95:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  9a:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  9f:	66 0f 58 c1          	addpd  xmm0,xmm1
  a3:	66 0f 58 d1          	addpd  xmm2,xmm1
  a7:	66 0f 58 d9          	addpd  xmm3,xmm1
  ab:	66 0f 58 e1          	addpd  xmm4,xmm1
  af:	66 0f 58 e9          	addpd  xmm5,xmm1
  b3:	66 0f 58 f1          	addpd  xmm6,xmm1
  b7:	66 0f 58 f9          	addpd  xmm7,xmm1
  bb:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  c0:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  c5:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  ca:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  cf:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  d4:	66 0f 58 c1          	addpd  xmm0,xmm1
  d8:	66 0f 58 d1          	addpd  xmm2,xmm1
  dc:	66 0f 58 d9          	addpd  xmm3,xmm1
  e0:	66 0f 58 e1          	addpd  xmm4,xmm1
  e4:	66 0f 58 e9          	addpd  xmm5,xmm1
  e8:	66 0f 58 f1          	addpd  xmm6,xmm1
  ec:	66 0f 58 f9          	addpd  xmm7,xmm1
  f0:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  f5:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  fa:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  ff:	66 44 0f 58 d9       	addpd  xmm11,xmm1
 104:	66 44 0f 58 e1       	addpd  xmm12,xmm1
 109:	66 0f 58 c1          	addpd  xmm0,xmm1
 10d:	66 0f 58 d1          	addpd  xmm2,xmm1
 111:	66 0f 58 d9          	addpd  xmm3,xmm1
 115:	66 0f 58 e1          	addpd  xmm4,xmm1
 119:	66 0f 58 e9          	addpd  xmm5,xmm1
 11d:	66 0f 58 f1          	addpd  xmm6,xmm1
 121:	66 0f 58 f9          	addpd  xmm7,xmm1
 125:	66 44 0f 58 c1       	addpd  xmm8,xmm1
 12a:	66 44 0f 58 c9       	addpd  xmm9,xmm1
 12f:	66 44 0f 58 d1       	addpd  xmm10,xmm1
 134:	66 44 0f 58 d9       	addpd  xmm11,xmm1
 139:	66 44 0f 58 e1       	addpd  xmm12,xmm1
 13e:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 73.0
- Core cycles: 38.0
- Reference cycles: 28.31
- UOPS_PORT_1: 36.0
- UOPS_PORT_0: 36.08

With blocking instructions for ports {'0', '5'}:

Code:

   0:	0f 6f c1             	movq   mm0,mm1
   3:	0f 6f d1             	movq   mm2,mm1
   6:	0f 6f d9             	movq   mm3,mm1
   9:	0f 6f e1             	movq   mm4,mm1
   c:	0f 6f e9             	movq   mm5,mm1
   f:	0f 6f f1             	movq   mm6,mm1
  12:	0f 6f f9             	movq   mm7,mm1
  15:	0f 6f c1             	movq   mm0,mm1
  18:	0f 6f d1             	movq   mm2,mm1
  1b:	0f 6f d9             	movq   mm3,mm1
  1e:	0f 6f e1             	movq   mm4,mm1
  21:	0f 6f e9             	movq   mm5,mm1
  24:	0f 6f f1             	movq   mm6,mm1
  27:	0f 6f f9             	movq   mm7,mm1
  2a:	0f 6f c1             	movq   mm0,mm1
  2d:	0f 6f d1             	movq   mm2,mm1
  30:	0f 6f d9             	movq   mm3,mm1
  33:	0f 6f e1             	movq   mm4,mm1
  36:	0f 6f e9             	movq   mm5,mm1
  39:	0f 6f f1             	movq   mm6,mm1
  3c:	0f 6f f9             	movq   mm7,mm1
  3f:	0f 6f c1             	movq   mm0,mm1
  42:	0f 6f d1             	movq   mm2,mm1
  45:	0f 6f d9             	movq   mm3,mm1
  48:	0f 6f e1             	movq   mm4,mm1
  4b:	0f 6f e9             	movq   mm5,mm1
  4e:	0f 6f f1             	movq   mm6,mm1
  51:	0f 6f f9             	movq   mm7,mm1
  54:	0f 6f c1             	movq   mm0,mm1
  57:	0f 6f d1             	movq   mm2,mm1
  5a:	0f 6f d9             	movq   mm3,mm1
  5d:	0f 6f e1             	movq   mm4,mm1
  60:	0f 6f e9             	movq   mm5,mm1
  63:	0f 6f f1             	movq   mm6,mm1
  66:	0f 6f f9             	movq   mm7,mm1
  69:	0f 6f c1             	movq   mm0,mm1
  6c:	0f 6f d1             	movq   mm2,mm1
  6f:	0f 6f d9             	movq   mm3,mm1
  72:	0f 6f e1             	movq   mm4,mm1
  75:	0f 6f e9             	movq   mm5,mm1
  78:	0f 6f f1             	movq   mm6,mm1
  7b:	0f 6f f9             	movq   mm7,mm1
  7e:	0f 6f c1             	movq   mm0,mm1
  81:	0f 6f d1             	movq   mm2,mm1
  84:	0f 6f d9             	movq   mm3,mm1
  87:	0f 6f e1             	movq   mm4,mm1
  8a:	0f 6f e9             	movq   mm5,mm1
  8d:	0f 6f f1             	movq   mm6,mm1
  90:	0f 6f f9             	movq   mm7,mm1
  93:	0f 6f c1             	movq   mm0,mm1
  96:	0f 6f d1             	movq   mm2,mm1
  99:	0f 6f d9             	movq   mm3,mm1
  9c:	0f 6f e1             	movq   mm4,mm1
  9f:	0f 6f e9             	movq   mm5,mm1
  a2:	0f 6f f1             	movq   mm6,mm1
  a5:	0f 6f f9             	movq   mm7,mm1
  a8:	0f 6f c1             	movq   mm0,mm1
  ab:	0f 6f d1             	movq   mm2,mm1
  ae:	0f 6f d9             	movq   mm3,mm1
  b1:	0f 6f e1             	movq   mm4,mm1
  b4:	0f 6f e9             	movq   mm5,mm1
  b7:	0f 6f f1             	movq   mm6,mm1
  ba:	0f 6f f9             	movq   mm7,mm1
  bd:	0f 6f c1             	movq   mm0,mm1
  c0:	0f 6f d1             	movq   mm2,mm1
  c3:	0f 6f d9             	movq   mm3,mm1
  c6:	0f 6f e1             	movq   mm4,mm1
  c9:	0f 6f e9             	movq   mm5,mm1
  cc:	0f 6f f1             	movq   mm6,mm1
  cf:	0f 6f f9             	movq   mm7,mm1
  d2:	0f 6f c1             	movq   mm0,mm1
  d5:	0f 6f d1             	movq   mm2,mm1
  d8:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Init:
```
PXOR MM1, MM1
```
Show nanoBench command
Results:
- Instructions retired: 73.0
- Core cycles: 37.92
- Reference cycles: 27.13
- UOPS_PORT_0: 36.0
- UOPS_PORT_5: 36.0

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 c1 c2 00          	rol    dx,0x0
  25:	66 41 c1 c0 00       	rol    r8w,0x0
  2a:	66 41 c1 c1 00       	rol    r9w,0x0
  2f:	66 41 c1 c2 00       	rol    r10w,0x0
  34:	66 41 c1 c3 00       	rol    r11w,0x0
  39:	66 41 c1 c4 00       	rol    r12w,0x0
  3e:	66 c1 c3 00          	rol    bx,0x0
  42:	66 c1 c1 00          	rol    cx,0x0
  46:	66 c1 c2 00          	rol    dx,0x0
  4a:	66 41 c1 c0 00       	rol    r8w,0x0
  4f:	66 41 c1 c1 00       	rol    r9w,0x0
  54:	66 41 c1 c2 00       	rol    r10w,0x0
  59:	66 41 c1 c3 00       	rol    r11w,0x0
  5e:	66 41 c1 c4 00       	rol    r12w,0x0
  63:	66 c1 c3 00          	rol    bx,0x0
  67:	66 c1 c1 00          	rol    cx,0x0
  6b:	66 c1 c2 00          	rol    dx,0x0
  6f:	66 41 c1 c0 00       	rol    r8w,0x0
  74:	66 41 c1 c1 00       	rol    r9w,0x0
  79:	66 41 c1 c2 00       	rol    r10w,0x0
  7e:	66 41 c1 c3 00       	rol    r11w,0x0
  83:	66 41 c1 c4 00       	rol    r12w,0x0
  88:	66 c1 c3 00          	rol    bx,0x0
  8c:	66 c1 c1 00          	rol    cx,0x0
  90:	66 c1 c2 00          	rol    dx,0x0
  94:	66 41 c1 c0 00       	rol    r8w,0x0
  99:	66 41 c1 c1 00       	rol    r9w,0x0
  9e:	66 41 c1 c2 00       	rol    r10w,0x0
  a3:	66 41 c1 c3 00       	rol    r11w,0x0
  a8:	66 41 c1 c4 00       	rol    r12w,0x0
  ad:	66 c1 c3 00          	rol    bx,0x0
  b1:	66 c1 c1 00          	rol    cx,0x0
  b5:	66 c1 c2 00          	rol    dx,0x0
  b9:	66 41 c1 c0 00       	rol    r8w,0x0
  be:	66 41 c1 c1 00       	rol    r9w,0x0
  c3:	66 41 c1 c2 00       	rol    r10w,0x0
  c8:	66 41 c1 c3 00       	rol    r11w,0x0
  cd:	66 41 c1 c4 00       	rol    r12w,0x0
  d2:	66 c1 c3 00          	rol    bx,0x0
  d6:	66 c1 c1 00          	rol    cx,0x0
  da:	66 c1 c2 00          	rol    dx,0x0
  de:	66 41 c1 c0 00       	rol    r8w,0x0
  e3:	66 41 c1 c1 00       	rol    r9w,0x0
  e8:	66 41 c1 c2 00       	rol    r10w,0x0
  ed:	66 41 c1 c3 00       	rol    r11w,0x0
  f2:	66 41 c1 c4 00       	rol    r12w,0x0
  f7:	66 c1 c3 00          	rol    bx,0x0
  fb:	66 c1 c1 00          	rol    cx,0x0
  ff:	66 c1 c2 00          	rol    dx,0x0
 103:	66 41 c1 c0 00       	rol    r8w,0x0
 108:	66 41 c1 c1 00       	rol    r9w,0x0
 10d:	66 41 c1 c2 00       	rol    r10w,0x0
 112:	66 41 c1 c3 00       	rol    r11w,0x0
 117:	66 41 c1 c4 00       	rol    r12w,0x0
 11c:	66 c1 c3 00          	rol    bx,0x0
 120:	66 c1 c1 00          	rol    cx,0x0
 124:	66 c1 c2 00          	rol    dx,0x0
 128:	66 41 c1 c0 00       	rol    r8w,0x0
 12d:	66 41 c1 c1 00       	rol    r9w,0x0
 132:	66 41 c1 c2 00       	rol    r10w,0x0
 137:	66 41 c1 c3 00       	rol    r11w,0x0
 13c:	66 41 c1 c4 00       	rol    r12w,0x0
 141:	66 c1 c3 00          	rol    bx,0x0
 145:	66 c1 c1 00          	rol    cx,0x0
 149:	66 c1 c2 00          	rol    dx,0x0
 14d:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 73.0
- Core cycles: 38.15
- Reference cycles: 30.67
- UOPS_PORT_6: 36.69
- UOPS_PORT_0: 36.23

⇨ One μop that can only use ports {'0', '6'}

With blocking instructions for ports {'1', '5'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	41 8d 16             	lea    edx,[r14]
  18:	45 8d 06             	lea    r8d,[r14]
  1b:	45 8d 0e             	lea    r9d,[r14]
  1e:	45 8d 16             	lea    r10d,[r14]
  21:	45 8d 1e             	lea    r11d,[r14]
  24:	45 8d 26             	lea    r12d,[r14]
  27:	41 8d 1e             	lea    ebx,[r14]
  2a:	41 8d 0e             	lea    ecx,[r14]
  2d:	41 8d 16             	lea    edx,[r14]
  30:	45 8d 06             	lea    r8d,[r14]
  33:	45 8d 0e             	lea    r9d,[r14]
  36:	45 8d 16             	lea    r10d,[r14]
  39:	45 8d 1e             	lea    r11d,[r14]
  3c:	45 8d 26             	lea    r12d,[r14]
  3f:	41 8d 1e             	lea    ebx,[r14]
  42:	41 8d 0e             	lea    ecx,[r14]
  45:	41 8d 16             	lea    edx,[r14]
  48:	45 8d 06             	lea    r8d,[r14]
  4b:	45 8d 0e             	lea    r9d,[r14]
  4e:	45 8d 16             	lea    r10d,[r14]
  51:	45 8d 1e             	lea    r11d,[r14]
  54:	45 8d 26             	lea    r12d,[r14]
  57:	41 8d 1e             	lea    ebx,[r14]
  5a:	41 8d 0e             	lea    ecx,[r14]
  5d:	41 8d 16             	lea    edx,[r14]
  60:	45 8d 06             	lea    r8d,[r14]
  63:	45 8d 0e             	lea    r9d,[r14]
  66:	45 8d 16             	lea    r10d,[r14]
  69:	45 8d 1e             	lea    r11d,[r14]
  6c:	45 8d 26             	lea    r12d,[r14]
  6f:	41 8d 1e             	lea    ebx,[r14]
  72:	41 8d 0e             	lea    ecx,[r14]
  75:	41 8d 16             	lea    edx,[r14]
  78:	45 8d 06             	lea    r8d,[r14]
  7b:	45 8d 0e             	lea    r9d,[r14]
  7e:	45 8d 16             	lea    r10d,[r14]
  81:	45 8d 1e             	lea    r11d,[r14]
  84:	45 8d 26             	lea    r12d,[r14]
  87:	41 8d 1e             	lea    ebx,[r14]
  8a:	41 8d 0e             	lea    ecx,[r14]
  8d:	41 8d 16             	lea    edx,[r14]
  90:	45 8d 06             	lea    r8d,[r14]
  93:	45 8d 0e             	lea    r9d,[r14]
  96:	45 8d 16             	lea    r10d,[r14]
  99:	45 8d 1e             	lea    r11d,[r14]
  9c:	45 8d 26             	lea    r12d,[r14]
  9f:	41 8d 1e             	lea    ebx,[r14]
  a2:	41 8d 0e             	lea    ecx,[r14]
  a5:	41 8d 16             	lea    edx,[r14]
  a8:	45 8d 06             	lea    r8d,[r14]
  ab:	45 8d 0e             	lea    r9d,[r14]
  ae:	45 8d 16             	lea    r10d,[r14]
  b1:	45 8d 1e             	lea    r11d,[r14]
  b4:	45 8d 26             	lea    r12d,[r14]
  b7:	41 8d 1e             	lea    ebx,[r14]
  ba:	41 8d 0e             	lea    ecx,[r14]
  bd:	41 8d 16             	lea    edx,[r14]
  c0:	45 8d 06             	lea    r8d,[r14]
  c3:	45 8d 0e             	lea    r9d,[r14]
  c6:	45 8d 16             	lea    r10d,[r14]
  c9:	45 8d 1e             	lea    r11d,[r14]
  cc:	45 8d 26             	lea    r12d,[r14]
  cf:	41 8d 1e             	lea    ebx,[r14]
  d2:	41 8d 0e             	lea    ecx,[r14]
  d5:	41 8d 16             	lea    edx,[r14]
  d8:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 73.0
- Core cycles: 37.54
- Reference cycles: 23.59
- UOPS_PORT_1: 36.0
- UOPS_PORT_5: 36.0

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  81:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  88:	00 00 
  8a:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  91:	00 00 
  93:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  9a:	00 00 
  9c:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  a3:	00 00 
  a5:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  ac:	00 00 
  ae:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  b5:	00 00 
  b7:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  be:	00 00 
  c0:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  c7:	00 00 
  c9:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  d0:	00 00 
  d2:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  d8:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  de:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  e4:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  ea:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  f1:	00 00 
  f3:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  fa:	00 00 
  fc:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 103:	00 00 
 105:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 10c:	00 00 
 10e:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 115:	00 00 
 117:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 11e:	00 00 
 120:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
 127:	00 00 
 129:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
 130:	00 00 
 132:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
 139:	00 00 
 13b:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 141:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 147:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
 14d:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
 153:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
 15a:	00 00 
 15c:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
 163:	00 00 
 165:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 16c:	00 00 
 16e:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 175:	00 00 
 177:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 17e:	00 00 
 180:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 187:	00 00 
 189:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
 190:	00 00 
 192:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
 199:	00 00 
 19b:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
 1a2:	00 00 
 1a4:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 1aa:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 1b0:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
 1b6:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
 1bc:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
 1c3:	00 00 
 1c5:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
 1cc:	00 00 
 1ce:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 1d5:	00 00 
 1d7:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 1de:	00 00 
 1e0:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 1e7:	00 00 
 1e9:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 1f0:	00 00 
 1f2:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
 1f9:	00 00 
 1fb:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
 202:	00 00 
 204:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
 20b:	00 00 
 20d:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 213:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 219:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
 21f:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
 225:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
 22c:	00 00 
 22e:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
 235:	00 00 
 237:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 23e:	00 00 
 240:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 73.0
- Core cycles: 39.0
- Reference cycles: 27.13
- UOPS_PORT_3: 37.04
- UOPS_PORT_2: 36.96

⇨ 2 μops that can only use ports {'2', '3'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  30:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  35:	66 0f 55 c1          	andnpd xmm0,xmm1
  39:	66 0f 55 d1          	andnpd xmm2,xmm1
  3d:	66 0f 55 d9          	andnpd xmm3,xmm1
  41:	66 0f 55 e1          	andnpd xmm4,xmm1
  45:	66 0f 55 e9          	andnpd xmm5,xmm1
  49:	66 0f 55 f1          	andnpd xmm6,xmm1
  4d:	66 0f 55 f9          	andnpd xmm7,xmm1
  51:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  56:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  5b:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  60:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  65:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  6a:	66 0f 55 c1          	andnpd xmm0,xmm1
  6e:	66 0f 55 d1          	andnpd xmm2,xmm1
  72:	66 0f 55 d9          	andnpd xmm3,xmm1
  76:	66 0f 55 e1          	andnpd xmm4,xmm1
  7a:	66 0f 55 e9          	andnpd xmm5,xmm1
  7e:	66 0f 55 f1          	andnpd xmm6,xmm1
  82:	66 0f 55 f9          	andnpd xmm7,xmm1
  86:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  8b:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  90:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  95:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  9a:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  9f:	66 0f 55 c1          	andnpd xmm0,xmm1
  a3:	66 0f 55 d1          	andnpd xmm2,xmm1
  a7:	66 0f 55 d9          	andnpd xmm3,xmm1
  ab:	66 0f 55 e1          	andnpd xmm4,xmm1
  af:	66 0f 55 e9          	andnpd xmm5,xmm1
  b3:	66 0f 55 f1          	andnpd xmm6,xmm1
  b7:	66 0f 55 f9          	andnpd xmm7,xmm1
  bb:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  c0:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  c5:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  ca:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  cf:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  d4:	66 0f 55 c1          	andnpd xmm0,xmm1
  d8:	66 0f 55 d1          	andnpd xmm2,xmm1
  dc:	66 0f 55 d9          	andnpd xmm3,xmm1
  e0:	66 0f 55 e1          	andnpd xmm4,xmm1
  e4:	66 0f 55 e9          	andnpd xmm5,xmm1
  e8:	66 0f 55 f1          	andnpd xmm6,xmm1
  ec:	66 0f 55 f9          	andnpd xmm7,xmm1
  f0:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  f5:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  fa:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  ff:	66 44 0f 55 d9       	andnpd xmm11,xmm1
 104:	66 44 0f 55 e1       	andnpd xmm12,xmm1
 109:	66 0f 55 c1          	andnpd xmm0,xmm1
 10d:	66 0f 55 d1          	andnpd xmm2,xmm1
 111:	66 0f 55 d9          	andnpd xmm3,xmm1
 115:	66 0f 55 e1          	andnpd xmm4,xmm1
 119:	66 0f 55 e9          	andnpd xmm5,xmm1
 11d:	66 0f 55 f1          	andnpd xmm6,xmm1
 121:	66 0f 55 f9          	andnpd xmm7,xmm1
 125:	66 44 0f 55 c1       	andnpd xmm8,xmm1
 12a:	66 44 0f 55 c9       	andnpd xmm9,xmm1
 12f:	66 44 0f 55 d1       	andnpd xmm10,xmm1
 134:	66 44 0f 55 d9       	andnpd xmm11,xmm1
 139:	66 44 0f 55 e1       	andnpd xmm12,xmm1
 13e:	66 0f 55 c1          	andnpd xmm0,xmm1
 142:	66 0f 55 d1          	andnpd xmm2,xmm1
 146:	66 0f 55 d9          	andnpd xmm3,xmm1
 14a:	66 0f 55 e1          	andnpd xmm4,xmm1
 14e:	66 0f 55 e9          	andnpd xmm5,xmm1
 152:	66 0f 55 f1          	andnpd xmm6,xmm1
 156:	66 0f 55 f9          	andnpd xmm7,xmm1
 15a:	66 44 0f 55 c1       	andnpd xmm8,xmm1
 15f:	66 44 0f 55 c9       	andnpd xmm9,xmm1
 164:	66 44 0f 55 d1       	andnpd xmm10,xmm1
 169:	66 44 0f 55 d9       	andnpd xmm11,xmm1
 16e:	66 44 0f 55 e1       	andnpd xmm12,xmm1
 173:	66 0f 55 c1          	andnpd xmm0,xmm1
 177:	66 0f 55 d1          	andnpd xmm2,xmm1
 17b:	66 0f 55 d9          	andnpd xmm3,xmm1
 17f:	66 0f 55 e1          	andnpd xmm4,xmm1
 183:	66 0f 55 e9          	andnpd xmm5,xmm1
 187:	66 0f 55 f1          	andnpd xmm6,xmm1
 18b:	66 0f 55 f9          	andnpd xmm7,xmm1
 18f:	66 44 0f 55 c1       	andnpd xmm8,xmm1
 194:	66 44 0f 55 c9       	andnpd xmm9,xmm1
 199:	66 44 0f 55 d1       	andnpd xmm10,xmm1
 19e:	66 44 0f 55 d9       	andnpd xmm11,xmm1
 1a3:	66 44 0f 55 e1       	andnpd xmm12,xmm1
 1a8:	66 0f 55 c1          	andnpd xmm0,xmm1
 1ac:	66 0f 55 d1          	andnpd xmm2,xmm1
 1b0:	66 0f 55 d9          	andnpd xmm3,xmm1
 1b4:	66 0f 55 e1          	andnpd xmm4,xmm1
 1b8:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 101.0
- Core cycles: 43.0
- Reference cycles: 29.13
- UOPS_PORT_1: 33.2
- UOPS_PORT_0: 32.9
- UOPS_PORT_5: 33.9

With blocking instructions for ports {'0', '1', '5', '6'}:

Code:

   0:	45 0f bf c1          	movsx  r8d,r9w
   4:	45 0f bf d1          	movsx  r10d,r9w
   8:	45 0f bf d9          	movsx  r11d,r9w
   c:	45 0f bf e1          	movsx  r12d,r9w
  10:	41 0f bf d9          	movsx  ebx,r9w
  14:	41 0f bf c9          	movsx  ecx,r9w
  18:	41 0f bf d1          	movsx  edx,r9w
  1c:	45 0f bf c1          	movsx  r8d,r9w
  20:	45 0f bf d1          	movsx  r10d,r9w
  24:	45 0f bf d9          	movsx  r11d,r9w
  28:	45 0f bf e1          	movsx  r12d,r9w
  2c:	41 0f bf d9          	movsx  ebx,r9w
  30:	41 0f bf c9          	movsx  ecx,r9w
  34:	41 0f bf d1          	movsx  edx,r9w
  38:	45 0f bf c1          	movsx  r8d,r9w
  3c:	45 0f bf d1          	movsx  r10d,r9w
  40:	45 0f bf d9          	movsx  r11d,r9w
  44:	45 0f bf e1          	movsx  r12d,r9w
  48:	41 0f bf d9          	movsx  ebx,r9w
  4c:	41 0f bf c9          	movsx  ecx,r9w
  50:	41 0f bf d1          	movsx  edx,r9w
  54:	45 0f bf c1          	movsx  r8d,r9w
  58:	45 0f bf d1          	movsx  r10d,r9w
  5c:	45 0f bf d9          	movsx  r11d,r9w
  60:	45 0f bf e1          	movsx  r12d,r9w
  64:	41 0f bf d9          	movsx  ebx,r9w
  68:	41 0f bf c9          	movsx  ecx,r9w
  6c:	41 0f bf d1          	movsx  edx,r9w
  70:	45 0f bf c1          	movsx  r8d,r9w
  74:	45 0f bf d1          	movsx  r10d,r9w
  78:	45 0f bf d9          	movsx  r11d,r9w
  7c:	45 0f bf e1          	movsx  r12d,r9w
  80:	41 0f bf d9          	movsx  ebx,r9w
  84:	41 0f bf c9          	movsx  ecx,r9w
  88:	41 0f bf d1          	movsx  edx,r9w
  8c:	45 0f bf c1          	movsx  r8d,r9w
  90:	45 0f bf d1          	movsx  r10d,r9w
  94:	45 0f bf d9          	movsx  r11d,r9w
  98:	45 0f bf e1          	movsx  r12d,r9w
  9c:	41 0f bf d9          	movsx  ebx,r9w
  a0:	41 0f bf c9          	movsx  ecx,r9w
  a4:	41 0f bf d1          	movsx  edx,r9w
  a8:	45 0f bf c1          	movsx  r8d,r9w
  ac:	45 0f bf d1          	movsx  r10d,r9w
  b0:	45 0f bf d9          	movsx  r11d,r9w
  b4:	45 0f bf e1          	movsx  r12d,r9w
  b8:	41 0f bf d9          	movsx  ebx,r9w
  bc:	41 0f bf c9          	movsx  ecx,r9w
  c0:	41 0f bf d1          	movsx  edx,r9w
  c4:	45 0f bf c1          	movsx  r8d,r9w
  c8:	45 0f bf d1          	movsx  r10d,r9w
  cc:	45 0f bf d9          	movsx  r11d,r9w
  d0:	45 0f bf e1          	movsx  r12d,r9w
  d4:	41 0f bf d9          	movsx  ebx,r9w
  d8:	41 0f bf c9          	movsx  ecx,r9w
  dc:	41 0f bf d1          	movsx  edx,r9w
  e0:	45 0f bf c1          	movsx  r8d,r9w
  e4:	45 0f bf d1          	movsx  r10d,r9w
  e8:	45 0f bf d9          	movsx  r11d,r9w
  ec:	45 0f bf e1          	movsx  r12d,r9w
  f0:	41 0f bf d9          	movsx  ebx,r9w
  f4:	41 0f bf c9          	movsx  ecx,r9w
  f8:	41 0f bf d1          	movsx  edx,r9w
  fc:	45 0f bf c1          	movsx  r8d,r9w
 100:	45 0f bf d1          	movsx  r10d,r9w
 104:	45 0f bf d9          	movsx  r11d,r9w
 108:	45 0f bf e1          	movsx  r12d,r9w
 10c:	41 0f bf d9          	movsx  ebx,r9w
 110:	41 0f bf c9          	movsx  ecx,r9w
 114:	41 0f bf d1          	movsx  edx,r9w
 118:	45 0f bf c1          	movsx  r8d,r9w
 11c:	45 0f bf d1          	movsx  r10d,r9w
 120:	45 0f bf d9          	movsx  r11d,r9w
 124:	45 0f bf e1          	movsx  r12d,r9w
 128:	41 0f bf d9          	movsx  ebx,r9w
 12c:	41 0f bf c9          	movsx  ecx,r9w
 130:	41 0f bf d1          	movsx  edx,r9w
 134:	45 0f bf c1          	movsx  r8d,r9w
 138:	45 0f bf d1          	movsx  r10d,r9w
 13c:	45 0f bf d9          	movsx  r11d,r9w
 140:	45 0f bf e1          	movsx  r12d,r9w
 144:	41 0f bf d9          	movsx  ebx,r9w
 148:	41 0f bf c9          	movsx  ecx,r9w
 14c:	41 0f bf d1          	movsx  edx,r9w
 150:	45 0f bf c1          	movsx  r8d,r9w
 154:	45 0f bf d1          	movsx  r10d,r9w
 158:	45 0f bf d9          	movsx  r11d,r9w
 15c:	45 0f bf e1          	movsx  r12d,r9w
 160:	41 0f bf d9          	movsx  ebx,r9w
 164:	41 0f bf c9          	movsx  ecx,r9w
 168:	41 0f bf d1          	movsx  edx,r9w
 16c:	45 0f bf c1          	movsx  r8d,r9w
 170:	45 0f bf d1          	movsx  r10d,r9w
 174:	45 0f bf d9          	movsx  r11d,r9w
 178:	45 0f bf e1          	movsx  r12d,r9w
 17c:	41 0f bf d9          	movsx  ebx,r9w
 180:	41 0f bf c9          	movsx  ecx,r9w
 184:	41 0f bf d1          	movsx  edx,r9w
 188:	45 0f bf c1          	movsx  r8d,r9w
 18c:	45 0f bf d1          	movsx  r10d,r9w
 190:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 101.0
- Core cycles: 41.8
- Reference cycles: 32.2
- UOPS_PORT_1: 25.4
- UOPS_PORT_6: 27.2
- UOPS_PORT_0: 24.9
- UOPS_PORT_5: 27.8

⇨ 4 μops that can only use ports {'0', '1', '5', '6'}

With an indexed addressing mode

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	0f 7e c2             	movd   edx,mm0
  1d:	41 0f 7e c0          	movd   r8d,mm0
  21:	41 0f 7e c1          	movd   r9d,mm0
  25:	41 0f 7e c2          	movd   r10d,mm0
  29:	41 0f 7e c3          	movd   r11d,mm0
  2d:	41 0f 7e c4          	movd   r12d,mm0
  31:	0f 7e c3             	movd   ebx,mm0
  34:	0f 7e c1             	movd   ecx,mm0
  37:	0f 7e c2             	movd   edx,mm0
  3a:	41 0f 7e c0          	movd   r8d,mm0
  3e:	41 0f 7e c1          	movd   r9d,mm0
  42:	41 0f 7e c2          	movd   r10d,mm0
  46:	41 0f 7e c3          	movd   r11d,mm0
  4a:	41 0f 7e c4          	movd   r12d,mm0
  4e:	0f 7e c3             	movd   ebx,mm0
  51:	0f 7e c1             	movd   ecx,mm0
  54:	0f 7e c2             	movd   edx,mm0
  57:	41 0f 7e c0          	movd   r8d,mm0
  5b:	41 0f 7e c1          	movd   r9d,mm0
  5f:	41 0f 7e c2          	movd   r10d,mm0
  63:	41 0f 7e c3          	movd   r11d,mm0
  67:	41 0f 7e c4          	movd   r12d,mm0
  6b:	0f 7e c3             	movd   ebx,mm0
  6e:	0f 7e c1             	movd   ecx,mm0
  71:	0f 7e c2             	movd   edx,mm0
  74:	41 0f 7e c0          	movd   r8d,mm0
  78:	41 0f 7e c1          	movd   r9d,mm0
  7c:	41 0f 7e c2          	movd   r10d,mm0
  80:	41 0f 7e c3          	movd   r11d,mm0
  84:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:
```
PXOR MM0, MM0;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 37.0
- Core cycles: 36.85
- Reference cycles: 24.99
- UOPS_PORT_0: 36.0

With blocking instructions for port '1':

Code:

   0:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
   7:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
   e:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  15:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  1c:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  23:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  2a:	66 f2 41 0f 38 f1 d1 	crc32  edx,r9w
  31:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  38:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  3f:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  46:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  4d:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  54:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  5b:	66 f2 41 0f 38 f1 d1 	crc32  edx,r9w
  62:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  69:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  70:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  77:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  7e:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  85:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  8c:	66 f2 41 0f 38 f1 d1 	crc32  edx,r9w
  93:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  9a:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  a1:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  a8:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  af:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  b6:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  bd:	66 f2 41 0f 38 f1 d1 	crc32  edx,r9w
  c4:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  cb:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  d2:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  d9:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  e0:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  e7:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  ee:	66 f2 41 0f 38 f1 d1 	crc32  edx,r9w
  f5:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  fc:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 37.0
- Core cycles: 36.81
- Reference cycles: 25.56
- UOPS_PORT_1: 36.0

With blocking instructions for port '4':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  35:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  3c:	4d 89 86 a0 00 00 00 	mov    QWORD PTR [r14+0xa0],r8
  43:	4d 89 86 a8 00 00 00 	mov    QWORD PTR [r14+0xa8],r8
  4a:	4d 89 86 b0 00 00 00 	mov    QWORD PTR [r14+0xb0],r8
  51:	4d 89 86 b8 00 00 00 	mov    QWORD PTR [r14+0xb8],r8
  58:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
  5c:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
  60:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
  64:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  68:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  6c:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  70:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  74:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  78:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  7f:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  86:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  8d:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  94:	4d 89 86 a0 00 00 00 	mov    QWORD PTR [r14+0xa0],r8
  9b:	4d 89 86 a8 00 00 00 	mov    QWORD PTR [r14+0xa8],r8
  a2:	4d 89 86 b0 00 00 00 	mov    QWORD PTR [r14+0xb0],r8
  a9:	4d 89 86 b8 00 00 00 	mov    QWORD PTR [r14+0xb8],r8
  b0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
  b4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
  b8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
  bc:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  c0:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 37.0
- Core cycles: 54.49
- Reference cycles: 37.48
- UOPS_PORT_4: 40.61

⇨ One μop that can only use port '4'

With blocking instructions for port '5':

Code:

   0:	66 0f 3a 21 c1 02    	insertps xmm0,xmm1,0x2
   6:	66 0f 3a 21 d1 02    	insertps xmm2,xmm1,0x2
   c:	66 0f 3a 21 d9 02    	insertps xmm3,xmm1,0x2
  12:	66 0f 3a 21 e1 02    	insertps xmm4,xmm1,0x2
  18:	66 0f 3a 21 e9 02    	insertps xmm5,xmm1,0x2
  1e:	66 0f 3a 21 f1 02    	insertps xmm6,xmm1,0x2
  24:	66 0f 3a 21 f9 02    	insertps xmm7,xmm1,0x2
  2a:	66 44 0f 3a 21 c1 02 	insertps xmm8,xmm1,0x2
  31:	66 44 0f 3a 21 c9 02 	insertps xmm9,xmm1,0x2
  38:	66 44 0f 3a 21 d1 02 	insertps xmm10,xmm1,0x2
  3f:	66 44 0f 3a 21 d9 02 	insertps xmm11,xmm1,0x2
  46:	66 44 0f 3a 21 e1 02 	insertps xmm12,xmm1,0x2
  4d:	66 0f 3a 21 c1 02    	insertps xmm0,xmm1,0x2
  53:	66 0f 3a 21 d1 02    	insertps xmm2,xmm1,0x2
  59:	66 0f 3a 21 d9 02    	insertps xmm3,xmm1,0x2
  5f:	66 0f 3a 21 e1 02    	insertps xmm4,xmm1,0x2
  65:	66 0f 3a 21 e9 02    	insertps xmm5,xmm1,0x2
  6b:	66 0f 3a 21 f1 02    	insertps xmm6,xmm1,0x2
  71:	66 0f 3a 21 f9 02    	insertps xmm7,xmm1,0x2
  77:	66 44 0f 3a 21 c1 02 	insertps xmm8,xmm1,0x2
  7e:	66 44 0f 3a 21 c9 02 	insertps xmm9,xmm1,0x2
  85:	66 44 0f 3a 21 d1 02 	insertps xmm10,xmm1,0x2
  8c:	66 44 0f 3a 21 d9 02 	insertps xmm11,xmm1,0x2
  93:	66 44 0f 3a 21 e1 02 	insertps xmm12,xmm1,0x2
  9a:	66 0f 3a 21 c1 02    	insertps xmm0,xmm1,0x2
  a0:	66 0f 3a 21 d1 02    	insertps xmm2,xmm1,0x2
  a6:	66 0f 3a 21 d9 02    	insertps xmm3,xmm1,0x2
  ac:	66 0f 3a 21 e1 02    	insertps xmm4,xmm1,0x2
  b2:	66 0f 3a 21 e9 02    	insertps xmm5,xmm1,0x2
  b8:	66 0f 3a 21 f1 02    	insertps xmm6,xmm1,0x2
  be:	66 0f 3a 21 f9 02    	insertps xmm7,xmm1,0x2
  c4:	66 44 0f 3a 21 c1 02 	insertps xmm8,xmm1,0x2
  cb:	66 44 0f 3a 21 c9 02 	insertps xmm9,xmm1,0x2
  d2:	66 44 0f 3a 21 d1 02 	insertps xmm10,xmm1,0x2
  d9:	66 44 0f 3a 21 d9 02 	insertps xmm11,xmm1,0x2
  e0:	66 44 0f 3a 21 e1 02 	insertps xmm12,xmm1,0x2
  e7:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 37.0
- Core cycles: 36.81
- Reference cycles: 27.26
- UOPS_PORT_5: 35.96

With blocking instructions for ports {'0', '1'}:

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  30:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  35:	66 0f 58 c1          	addpd  xmm0,xmm1
  39:	66 0f 58 d1          	addpd  xmm2,xmm1
  3d:	66 0f 58 d9          	addpd  xmm3,xmm1
  41:	66 0f 58 e1          	addpd  xmm4,xmm1
  45:	66 0f 58 e9          	addpd  xmm5,xmm1
  49:	66 0f 58 f1          	addpd  xmm6,xmm1
  4d:	66 0f 58 f9          	addpd  xmm7,xmm1
  51:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  56:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  5b:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  60:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  65:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  6a:	66 0f 58 c1          	addpd  xmm0,xmm1
  6e:	66 0f 58 d1          	addpd  xmm2,xmm1
  72:	66 0f 58 d9          	addpd  xmm3,xmm1
  76:	66 0f 58 e1          	addpd  xmm4,xmm1
  7a:	66 0f 58 e9          	addpd  xmm5,xmm1
  7e:	66 0f 58 f1          	addpd  xmm6,xmm1
  82:	66 0f 58 f9          	addpd  xmm7,xmm1
  86:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  8b:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  90:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  95:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  9a:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  9f:	66 0f 58 c1          	addpd  xmm0,xmm1
  a3:	66 0f 58 d1          	addpd  xmm2,xmm1
  a7:	66 0f 58 d9          	addpd  xmm3,xmm1
  ab:	66 0f 58 e1          	addpd  xmm4,xmm1
  af:	66 0f 58 e9          	addpd  xmm5,xmm1
  b3:	66 0f 58 f1          	addpd  xmm6,xmm1
  b7:	66 0f 58 f9          	addpd  xmm7,xmm1
  bb:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  c0:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  c5:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  ca:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  cf:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  d4:	66 0f 58 c1          	addpd  xmm0,xmm1
  d8:	66 0f 58 d1          	addpd  xmm2,xmm1
  dc:	66 0f 58 d9          	addpd  xmm3,xmm1
  e0:	66 0f 58 e1          	addpd  xmm4,xmm1
  e4:	66 0f 58 e9          	addpd  xmm5,xmm1
  e8:	66 0f 58 f1          	addpd  xmm6,xmm1
  ec:	66 0f 58 f9          	addpd  xmm7,xmm1
  f0:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  f5:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  fa:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  ff:	66 44 0f 58 d9       	addpd  xmm11,xmm1
 104:	66 44 0f 58 e1       	addpd  xmm12,xmm1
 109:	66 0f 58 c1          	addpd  xmm0,xmm1
 10d:	66 0f 58 d1          	addpd  xmm2,xmm1
 111:	66 0f 58 d9          	addpd  xmm3,xmm1
 115:	66 0f 58 e1          	addpd  xmm4,xmm1
 119:	66 0f 58 e9          	addpd  xmm5,xmm1
 11d:	66 0f 58 f1          	addpd  xmm6,xmm1
 121:	66 0f 58 f9          	addpd  xmm7,xmm1
 125:	66 44 0f 58 c1       	addpd  xmm8,xmm1
 12a:	66 44 0f 58 c9       	addpd  xmm9,xmm1
 12f:	66 44 0f 58 d1       	addpd  xmm10,xmm1
 134:	66 44 0f 58 d9       	addpd  xmm11,xmm1
 139:	66 44 0f 58 e1       	addpd  xmm12,xmm1
 13e:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 73.0
- Core cycles: 38.0
- Reference cycles: 27.13
- UOPS_PORT_1: 36.0
- UOPS_PORT_0: 36.08

With blocking instructions for ports {'0', '5'}:

Code:

   0:	0f 6f c1             	movq   mm0,mm1
   3:	0f 6f d1             	movq   mm2,mm1
   6:	0f 6f d9             	movq   mm3,mm1
   9:	0f 6f e1             	movq   mm4,mm1
   c:	0f 6f e9             	movq   mm5,mm1
   f:	0f 6f f1             	movq   mm6,mm1
  12:	0f 6f f9             	movq   mm7,mm1
  15:	0f 6f c1             	movq   mm0,mm1
  18:	0f 6f d1             	movq   mm2,mm1
  1b:	0f 6f d9             	movq   mm3,mm1
  1e:	0f 6f e1             	movq   mm4,mm1
  21:	0f 6f e9             	movq   mm5,mm1
  24:	0f 6f f1             	movq   mm6,mm1
  27:	0f 6f f9             	movq   mm7,mm1
  2a:	0f 6f c1             	movq   mm0,mm1
  2d:	0f 6f d1             	movq   mm2,mm1
  30:	0f 6f d9             	movq   mm3,mm1
  33:	0f 6f e1             	movq   mm4,mm1
  36:	0f 6f e9             	movq   mm5,mm1
  39:	0f 6f f1             	movq   mm6,mm1
  3c:	0f 6f f9             	movq   mm7,mm1
  3f:	0f 6f c1             	movq   mm0,mm1
  42:	0f 6f d1             	movq   mm2,mm1
  45:	0f 6f d9             	movq   mm3,mm1
  48:	0f 6f e1             	movq   mm4,mm1
  4b:	0f 6f e9             	movq   mm5,mm1
  4e:	0f 6f f1             	movq   mm6,mm1
  51:	0f 6f f9             	movq   mm7,mm1
  54:	0f 6f c1             	movq   mm0,mm1
  57:	0f 6f d1             	movq   mm2,mm1
  5a:	0f 6f d9             	movq   mm3,mm1
  5d:	0f 6f e1             	movq   mm4,mm1
  60:	0f 6f e9             	movq   mm5,mm1
  63:	0f 6f f1             	movq   mm6,mm1
  66:	0f 6f f9             	movq   mm7,mm1
  69:	0f 6f c1             	movq   mm0,mm1
  6c:	0f 6f d1             	movq   mm2,mm1
  6f:	0f 6f d9             	movq   mm3,mm1
  72:	0f 6f e1             	movq   mm4,mm1
  75:	0f 6f e9             	movq   mm5,mm1
  78:	0f 6f f1             	movq   mm6,mm1
  7b:	0f 6f f9             	movq   mm7,mm1
  7e:	0f 6f c1             	movq   mm0,mm1
  81:	0f 6f d1             	movq   mm2,mm1
  84:	0f 6f d9             	movq   mm3,mm1
  87:	0f 6f e1             	movq   mm4,mm1
  8a:	0f 6f e9             	movq   mm5,mm1
  8d:	0f 6f f1             	movq   mm6,mm1
  90:	0f 6f f9             	movq   mm7,mm1
  93:	0f 6f c1             	movq   mm0,mm1
  96:	0f 6f d1             	movq   mm2,mm1
  99:	0f 6f d9             	movq   mm3,mm1
  9c:	0f 6f e1             	movq   mm4,mm1
  9f:	0f 6f e9             	movq   mm5,mm1
  a2:	0f 6f f1             	movq   mm6,mm1
  a5:	0f 6f f9             	movq   mm7,mm1
  a8:	0f 6f c1             	movq   mm0,mm1
  ab:	0f 6f d1             	movq   mm2,mm1
  ae:	0f 6f d9             	movq   mm3,mm1
  b1:	0f 6f e1             	movq   mm4,mm1
  b4:	0f 6f e9             	movq   mm5,mm1
  b7:	0f 6f f1             	movq   mm6,mm1
  ba:	0f 6f f9             	movq   mm7,mm1
  bd:	0f 6f c1             	movq   mm0,mm1
  c0:	0f 6f d1             	movq   mm2,mm1
  c3:	0f 6f d9             	movq   mm3,mm1
  c6:	0f 6f e1             	movq   mm4,mm1
  c9:	0f 6f e9             	movq   mm5,mm1
  cc:	0f 6f f1             	movq   mm6,mm1
  cf:	0f 6f f9             	movq   mm7,mm1
  d2:	0f 6f c1             	movq   mm0,mm1
  d5:	0f 6f d1             	movq   mm2,mm1
  d8:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:
```
PXOR MM1, MM1;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 73.0
- Core cycles: 37.92
- Reference cycles: 27.13
- UOPS_PORT_0: 36.0
- UOPS_PORT_5: 36.0

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 c1 c2 00          	rol    dx,0x0
  25:	66 41 c1 c0 00       	rol    r8w,0x0
  2a:	66 41 c1 c1 00       	rol    r9w,0x0
  2f:	66 41 c1 c2 00       	rol    r10w,0x0
  34:	66 41 c1 c3 00       	rol    r11w,0x0
  39:	66 41 c1 c4 00       	rol    r12w,0x0
  3e:	66 c1 c3 00          	rol    bx,0x0
  42:	66 c1 c1 00          	rol    cx,0x0
  46:	66 c1 c2 00          	rol    dx,0x0
  4a:	66 41 c1 c0 00       	rol    r8w,0x0
  4f:	66 41 c1 c1 00       	rol    r9w,0x0
  54:	66 41 c1 c2 00       	rol    r10w,0x0
  59:	66 41 c1 c3 00       	rol    r11w,0x0
  5e:	66 41 c1 c4 00       	rol    r12w,0x0
  63:	66 c1 c3 00          	rol    bx,0x0
  67:	66 c1 c1 00          	rol    cx,0x0
  6b:	66 c1 c2 00          	rol    dx,0x0
  6f:	66 41 c1 c0 00       	rol    r8w,0x0
  74:	66 41 c1 c1 00       	rol    r9w,0x0
  79:	66 41 c1 c2 00       	rol    r10w,0x0
  7e:	66 41 c1 c3 00       	rol    r11w,0x0
  83:	66 41 c1 c4 00       	rol    r12w,0x0
  88:	66 c1 c3 00          	rol    bx,0x0
  8c:	66 c1 c1 00          	rol    cx,0x0
  90:	66 c1 c2 00          	rol    dx,0x0
  94:	66 41 c1 c0 00       	rol    r8w,0x0
  99:	66 41 c1 c1 00       	rol    r9w,0x0
  9e:	66 41 c1 c2 00       	rol    r10w,0x0
  a3:	66 41 c1 c3 00       	rol    r11w,0x0
  a8:	66 41 c1 c4 00       	rol    r12w,0x0
  ad:	66 c1 c3 00          	rol    bx,0x0
  b1:	66 c1 c1 00          	rol    cx,0x0
  b5:	66 c1 c2 00          	rol    dx,0x0
  b9:	66 41 c1 c0 00       	rol    r8w,0x0
  be:	66 41 c1 c1 00       	rol    r9w,0x0
  c3:	66 41 c1 c2 00       	rol    r10w,0x0
  c8:	66 41 c1 c3 00       	rol    r11w,0x0
  cd:	66 41 c1 c4 00       	rol    r12w,0x0
  d2:	66 c1 c3 00          	rol    bx,0x0
  d6:	66 c1 c1 00          	rol    cx,0x0
  da:	66 c1 c2 00          	rol    dx,0x0
  de:	66 41 c1 c0 00       	rol    r8w,0x0
  e3:	66 41 c1 c1 00       	rol    r9w,0x0
  e8:	66 41 c1 c2 00       	rol    r10w,0x0
  ed:	66 41 c1 c3 00       	rol    r11w,0x0
  f2:	66 41 c1 c4 00       	rol    r12w,0x0
  f7:	66 c1 c3 00          	rol    bx,0x0
  fb:	66 c1 c1 00          	rol    cx,0x0
  ff:	66 c1 c2 00          	rol    dx,0x0
 103:	66 41 c1 c0 00       	rol    r8w,0x0
 108:	66 41 c1 c1 00       	rol    r9w,0x0
 10d:	66 41 c1 c2 00       	rol    r10w,0x0
 112:	66 41 c1 c3 00       	rol    r11w,0x0
 117:	66 41 c1 c4 00       	rol    r12w,0x0
 11c:	66 c1 c3 00          	rol    bx,0x0
 120:	66 c1 c1 00          	rol    cx,0x0
 124:	66 c1 c2 00          	rol    dx,0x0
 128:	66 41 c1 c0 00       	rol    r8w,0x0
 12d:	66 41 c1 c1 00       	rol    r9w,0x0
 132:	66 41 c1 c2 00       	rol    r10w,0x0
 137:	66 41 c1 c3 00       	rol    r11w,0x0
 13c:	66 41 c1 c4 00       	rol    r12w,0x0
 141:	66 c1 c3 00          	rol    bx,0x0
 145:	66 c1 c1 00          	rol    cx,0x0
 149:	66 c1 c2 00          	rol    dx,0x0
 14d:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 73.0
- Core cycles: 38.15
- Reference cycles: 28.31
- UOPS_PORT_6: 36.69
- UOPS_PORT_0: 36.23

⇨ One μop that can only use ports {'0', '6'}

With blocking instructions for ports {'1', '5'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	41 8d 16             	lea    edx,[r14]
  18:	45 8d 06             	lea    r8d,[r14]
  1b:	45 8d 0e             	lea    r9d,[r14]
  1e:	45 8d 16             	lea    r10d,[r14]
  21:	45 8d 1e             	lea    r11d,[r14]
  24:	45 8d 26             	lea    r12d,[r14]
  27:	41 8d 1e             	lea    ebx,[r14]
  2a:	41 8d 0e             	lea    ecx,[r14]
  2d:	41 8d 16             	lea    edx,[r14]
  30:	45 8d 06             	lea    r8d,[r14]
  33:	45 8d 0e             	lea    r9d,[r14]
  36:	45 8d 16             	lea    r10d,[r14]
  39:	45 8d 1e             	lea    r11d,[r14]
  3c:	45 8d 26             	lea    r12d,[r14]
  3f:	41 8d 1e             	lea    ebx,[r14]
  42:	41 8d 0e             	lea    ecx,[r14]
  45:	41 8d 16             	lea    edx,[r14]
  48:	45 8d 06             	lea    r8d,[r14]
  4b:	45 8d 0e             	lea    r9d,[r14]
  4e:	45 8d 16             	lea    r10d,[r14]
  51:	45 8d 1e             	lea    r11d,[r14]
  54:	45 8d 26             	lea    r12d,[r14]
  57:	41 8d 1e             	lea    ebx,[r14]
  5a:	41 8d 0e             	lea    ecx,[r14]
  5d:	41 8d 16             	lea    edx,[r14]
  60:	45 8d 06             	lea    r8d,[r14]
  63:	45 8d 0e             	lea    r9d,[r14]
  66:	45 8d 16             	lea    r10d,[r14]
  69:	45 8d 1e             	lea    r11d,[r14]
  6c:	45 8d 26             	lea    r12d,[r14]
  6f:	41 8d 1e             	lea    ebx,[r14]
  72:	41 8d 0e             	lea    ecx,[r14]
  75:	41 8d 16             	lea    edx,[r14]
  78:	45 8d 06             	lea    r8d,[r14]
  7b:	45 8d 0e             	lea    r9d,[r14]
  7e:	45 8d 16             	lea    r10d,[r14]
  81:	45 8d 1e             	lea    r11d,[r14]
  84:	45 8d 26             	lea    r12d,[r14]
  87:	41 8d 1e             	lea    ebx,[r14]
  8a:	41 8d 0e             	lea    ecx,[r14]
  8d:	41 8d 16             	lea    edx,[r14]
  90:	45 8d 06             	lea    r8d,[r14]
  93:	45 8d 0e             	lea    r9d,[r14]
  96:	45 8d 16             	lea    r10d,[r14]
  99:	45 8d 1e             	lea    r11d,[r14]
  9c:	45 8d 26             	lea    r12d,[r14]
  9f:	41 8d 1e             	lea    ebx,[r14]
  a2:	41 8d 0e             	lea    ecx,[r14]
  a5:	41 8d 16             	lea    edx,[r14]
  a8:	45 8d 06             	lea    r8d,[r14]
  ab:	45 8d 0e             	lea    r9d,[r14]
  ae:	45 8d 16             	lea    r10d,[r14]
  b1:	45 8d 1e             	lea    r11d,[r14]
  b4:	45 8d 26             	lea    r12d,[r14]
  b7:	41 8d 1e             	lea    ebx,[r14]
  ba:	41 8d 0e             	lea    ecx,[r14]
  bd:	41 8d 16             	lea    edx,[r14]
  c0:	45 8d 06             	lea    r8d,[r14]
  c3:	45 8d 0e             	lea    r9d,[r14]
  c6:	45 8d 16             	lea    r10d,[r14]
  c9:	45 8d 1e             	lea    r11d,[r14]
  cc:	45 8d 26             	lea    r12d,[r14]
  cf:	41 8d 1e             	lea    ebx,[r14]
  d2:	41 8d 0e             	lea    ecx,[r14]
  d5:	41 8d 16             	lea    edx,[r14]
  d8:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 73.0
- Core cycles: 37.54
- Reference cycles: 22.41
- UOPS_PORT_1: 36.0
- UOPS_PORT_5: 36.0

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  81:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  88:	00 00 
  8a:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  91:	00 00 
  93:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  9a:	00 00 
  9c:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  a3:	00 00 
  a5:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  ac:	00 00 
  ae:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  b5:	00 00 
  b7:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  be:	00 00 
  c0:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  c7:	00 00 
  c9:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  d0:	00 00 
  d2:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  d8:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  de:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  e4:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  ea:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  f1:	00 00 
  f3:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  fa:	00 00 
  fc:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 103:	00 00 
 105:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 10c:	00 00 
 10e:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 115:	00 00 
 117:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 11e:	00 00 
 120:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
 127:	00 00 
 129:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
 130:	00 00 
 132:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
 139:	00 00 
 13b:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 141:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 147:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
 14d:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
 153:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
 15a:	00 00 
 15c:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
 163:	00 00 
 165:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 16c:	00 00 
 16e:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 175:	00 00 
 177:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 17e:	00 00 
 180:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 187:	00 00 
 189:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
 190:	00 00 
 192:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
 199:	00 00 
 19b:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
 1a2:	00 00 
 1a4:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 1aa:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 1b0:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
 1b6:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
 1bc:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
 1c3:	00 00 
 1c5:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
 1cc:	00 00 
 1ce:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 1d5:	00 00 
 1d7:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 1de:	00 00 
 1e0:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 1e7:	00 00 
 1e9:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 1f0:	00 00 
 1f2:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
 1f9:	00 00 
 1fb:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
 202:	00 00 
 204:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
 20b:	00 00 
 20d:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 213:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 219:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
 21f:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
 225:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
 22c:	00 00 
 22e:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
 235:	00 00 
 237:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 23e:	00 00 
 240:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 73.0
- Core cycles: 39.0
- Reference cycles: 28.31
- UOPS_PORT_3: 36.96
- UOPS_PORT_2: 37.04

⇨ 2 μops that can only use ports {'2', '3'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  30:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  35:	66 0f 55 c1          	andnpd xmm0,xmm1
  39:	66 0f 55 d1          	andnpd xmm2,xmm1
  3d:	66 0f 55 d9          	andnpd xmm3,xmm1
  41:	66 0f 55 e1          	andnpd xmm4,xmm1
  45:	66 0f 55 e9          	andnpd xmm5,xmm1
  49:	66 0f 55 f1          	andnpd xmm6,xmm1
  4d:	66 0f 55 f9          	andnpd xmm7,xmm1
  51:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  56:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  5b:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  60:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  65:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  6a:	66 0f 55 c1          	andnpd xmm0,xmm1
  6e:	66 0f 55 d1          	andnpd xmm2,xmm1
  72:	66 0f 55 d9          	andnpd xmm3,xmm1
  76:	66 0f 55 e1          	andnpd xmm4,xmm1
  7a:	66 0f 55 e9          	andnpd xmm5,xmm1
  7e:	66 0f 55 f1          	andnpd xmm6,xmm1
  82:	66 0f 55 f9          	andnpd xmm7,xmm1
  86:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  8b:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  90:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  95:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  9a:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  9f:	66 0f 55 c1          	andnpd xmm0,xmm1
  a3:	66 0f 55 d1          	andnpd xmm2,xmm1
  a7:	66 0f 55 d9          	andnpd xmm3,xmm1
  ab:	66 0f 55 e1          	andnpd xmm4,xmm1
  af:	66 0f 55 e9          	andnpd xmm5,xmm1
  b3:	66 0f 55 f1          	andnpd xmm6,xmm1
  b7:	66 0f 55 f9          	andnpd xmm7,xmm1
  bb:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  c0:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  c5:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  ca:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  cf:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  d4:	66 0f 55 c1          	andnpd xmm0,xmm1
  d8:	66 0f 55 d1          	andnpd xmm2,xmm1
  dc:	66 0f 55 d9          	andnpd xmm3,xmm1
  e0:	66 0f 55 e1          	andnpd xmm4,xmm1
  e4:	66 0f 55 e9          	andnpd xmm5,xmm1
  e8:	66 0f 55 f1          	andnpd xmm6,xmm1
  ec:	66 0f 55 f9          	andnpd xmm7,xmm1
  f0:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  f5:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  fa:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  ff:	66 44 0f 55 d9       	andnpd xmm11,xmm1
 104:	66 44 0f 55 e1       	andnpd xmm12,xmm1
 109:	66 0f 55 c1          	andnpd xmm0,xmm1
 10d:	66 0f 55 d1          	andnpd xmm2,xmm1
 111:	66 0f 55 d9          	andnpd xmm3,xmm1
 115:	66 0f 55 e1          	andnpd xmm4,xmm1
 119:	66 0f 55 e9          	andnpd xmm5,xmm1
 11d:	66 0f 55 f1          	andnpd xmm6,xmm1
 121:	66 0f 55 f9          	andnpd xmm7,xmm1
 125:	66 44 0f 55 c1       	andnpd xmm8,xmm1
 12a:	66 44 0f 55 c9       	andnpd xmm9,xmm1
 12f:	66 44 0f 55 d1       	andnpd xmm10,xmm1
 134:	66 44 0f 55 d9       	andnpd xmm11,xmm1
 139:	66 44 0f 55 e1       	andnpd xmm12,xmm1
 13e:	66 0f 55 c1          	andnpd xmm0,xmm1
 142:	66 0f 55 d1          	andnpd xmm2,xmm1
 146:	66 0f 55 d9          	andnpd xmm3,xmm1
 14a:	66 0f 55 e1          	andnpd xmm4,xmm1
 14e:	66 0f 55 e9          	andnpd xmm5,xmm1
 152:	66 0f 55 f1          	andnpd xmm6,xmm1
 156:	66 0f 55 f9          	andnpd xmm7,xmm1
 15a:	66 44 0f 55 c1       	andnpd xmm8,xmm1
 15f:	66 44 0f 55 c9       	andnpd xmm9,xmm1
 164:	66 44 0f 55 d1       	andnpd xmm10,xmm1
 169:	66 44 0f 55 d9       	andnpd xmm11,xmm1
 16e:	66 44 0f 55 e1       	andnpd xmm12,xmm1
 173:	66 0f 55 c1          	andnpd xmm0,xmm1
 177:	66 0f 55 d1          	andnpd xmm2,xmm1
 17b:	66 0f 55 d9          	andnpd xmm3,xmm1
 17f:	66 0f 55 e1          	andnpd xmm4,xmm1
 183:	66 0f 55 e9          	andnpd xmm5,xmm1
 187:	66 0f 55 f1          	andnpd xmm6,xmm1
 18b:	66 0f 55 f9          	andnpd xmm7,xmm1
 18f:	66 44 0f 55 c1       	andnpd xmm8,xmm1
 194:	66 44 0f 55 c9       	andnpd xmm9,xmm1
 199:	66 44 0f 55 d1       	andnpd xmm10,xmm1
 19e:	66 44 0f 55 d9       	andnpd xmm11,xmm1
 1a3:	66 44 0f 55 e1       	andnpd xmm12,xmm1
 1a8:	66 0f 55 c1          	andnpd xmm0,xmm1
 1ac:	66 0f 55 d1          	andnpd xmm2,xmm1
 1b0:	66 0f 55 d9          	andnpd xmm3,xmm1
 1b4:	66 0f 55 e1          	andnpd xmm4,xmm1
 1b8:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 101.0
- Core cycles: 43.0
- Reference cycles: 36.8
- UOPS_PORT_1: 33.2
- UOPS_PORT_0: 32.9
- UOPS_PORT_5: 33.9

With blocking instructions for ports {'0', '1', '5', '6'}:

Code:

   0:	45 0f bf c1          	movsx  r8d,r9w
   4:	45 0f bf d1          	movsx  r10d,r9w
   8:	45 0f bf d9          	movsx  r11d,r9w
   c:	45 0f bf e1          	movsx  r12d,r9w
  10:	41 0f bf d9          	movsx  ebx,r9w
  14:	41 0f bf c9          	movsx  ecx,r9w
  18:	41 0f bf d1          	movsx  edx,r9w
  1c:	45 0f bf c1          	movsx  r8d,r9w
  20:	45 0f bf d1          	movsx  r10d,r9w
  24:	45 0f bf d9          	movsx  r11d,r9w
  28:	45 0f bf e1          	movsx  r12d,r9w
  2c:	41 0f bf d9          	movsx  ebx,r9w
  30:	41 0f bf c9          	movsx  ecx,r9w
  34:	41 0f bf d1          	movsx  edx,r9w
  38:	45 0f bf c1          	movsx  r8d,r9w
  3c:	45 0f bf d1          	movsx  r10d,r9w
  40:	45 0f bf d9          	movsx  r11d,r9w
  44:	45 0f bf e1          	movsx  r12d,r9w
  48:	41 0f bf d9          	movsx  ebx,r9w
  4c:	41 0f bf c9          	movsx  ecx,r9w
  50:	41 0f bf d1          	movsx  edx,r9w
  54:	45 0f bf c1          	movsx  r8d,r9w
  58:	45 0f bf d1          	movsx  r10d,r9w
  5c:	45 0f bf d9          	movsx  r11d,r9w
  60:	45 0f bf e1          	movsx  r12d,r9w
  64:	41 0f bf d9          	movsx  ebx,r9w
  68:	41 0f bf c9          	movsx  ecx,r9w
  6c:	41 0f bf d1          	movsx  edx,r9w
  70:	45 0f bf c1          	movsx  r8d,r9w
  74:	45 0f bf d1          	movsx  r10d,r9w
  78:	45 0f bf d9          	movsx  r11d,r9w
  7c:	45 0f bf e1          	movsx  r12d,r9w
  80:	41 0f bf d9          	movsx  ebx,r9w
  84:	41 0f bf c9          	movsx  ecx,r9w
  88:	41 0f bf d1          	movsx  edx,r9w
  8c:	45 0f bf c1          	movsx  r8d,r9w
  90:	45 0f bf d1          	movsx  r10d,r9w
  94:	45 0f bf d9          	movsx  r11d,r9w
  98:	45 0f bf e1          	movsx  r12d,r9w
  9c:	41 0f bf d9          	movsx  ebx,r9w
  a0:	41 0f bf c9          	movsx  ecx,r9w
  a4:	41 0f bf d1          	movsx  edx,r9w
  a8:	45 0f bf c1          	movsx  r8d,r9w
  ac:	45 0f bf d1          	movsx  r10d,r9w
  b0:	45 0f bf d9          	movsx  r11d,r9w
  b4:	45 0f bf e1          	movsx  r12d,r9w
  b8:	41 0f bf d9          	movsx  ebx,r9w
  bc:	41 0f bf c9          	movsx  ecx,r9w
  c0:	41 0f bf d1          	movsx  edx,r9w
  c4:	45 0f bf c1          	movsx  r8d,r9w
  c8:	45 0f bf d1          	movsx  r10d,r9w
  cc:	45 0f bf d9          	movsx  r11d,r9w
  d0:	45 0f bf e1          	movsx  r12d,r9w
  d4:	41 0f bf d9          	movsx  ebx,r9w
  d8:	41 0f bf c9          	movsx  ecx,r9w
  dc:	41 0f bf d1          	movsx  edx,r9w
  e0:	45 0f bf c1          	movsx  r8d,r9w
  e4:	45 0f bf d1          	movsx  r10d,r9w
  e8:	45 0f bf d9          	movsx  r11d,r9w
  ec:	45 0f bf e1          	movsx  r12d,r9w
  f0:	41 0f bf d9          	movsx  ebx,r9w
  f4:	41 0f bf c9          	movsx  ecx,r9w
  f8:	41 0f bf d1          	movsx  edx,r9w
  fc:	45 0f bf c1          	movsx  r8d,r9w
 100:	45 0f bf d1          	movsx  r10d,r9w
 104:	45 0f bf d9          	movsx  r11d,r9w
 108:	45 0f bf e1          	movsx  r12d,r9w
 10c:	41 0f bf d9          	movsx  ebx,r9w
 110:	41 0f bf c9          	movsx  ecx,r9w
 114:	41 0f bf d1          	movsx  edx,r9w
 118:	45 0f bf c1          	movsx  r8d,r9w
 11c:	45 0f bf d1          	movsx  r10d,r9w
 120:	45 0f bf d9          	movsx  r11d,r9w
 124:	45 0f bf e1          	movsx  r12d,r9w
 128:	41 0f bf d9          	movsx  ebx,r9w
 12c:	41 0f bf c9          	movsx  ecx,r9w
 130:	41 0f bf d1          	movsx  edx,r9w
 134:	45 0f bf c1          	movsx  r8d,r9w
 138:	45 0f bf d1          	movsx  r10d,r9w
 13c:	45 0f bf d9          	movsx  r11d,r9w
 140:	45 0f bf e1          	movsx  r12d,r9w
 144:	41 0f bf d9          	movsx  ebx,r9w
 148:	41 0f bf c9          	movsx  ecx,r9w
 14c:	41 0f bf d1          	movsx  edx,r9w
 150:	45 0f bf c1          	movsx  r8d,r9w
 154:	45 0f bf d1          	movsx  r10d,r9w
 158:	45 0f bf d9          	movsx  r11d,r9w
 15c:	45 0f bf e1          	movsx  r12d,r9w
 160:	41 0f bf d9          	movsx  ebx,r9w
 164:	41 0f bf c9          	movsx  ecx,r9w
 168:	41 0f bf d1          	movsx  edx,r9w
 16c:	45 0f bf c1          	movsx  r8d,r9w
 170:	45 0f bf d1          	movsx  r10d,r9w
 174:	45 0f bf d9          	movsx  r11d,r9w
 178:	45 0f bf e1          	movsx  r12d,r9w
 17c:	41 0f bf d9          	movsx  ebx,r9w
 180:	41 0f bf c9          	movsx  ecx,r9w
 184:	41 0f bf d1          	movsx  edx,r9w
 188:	45 0f bf c1          	movsx  r8d,r9w
 18c:	45 0f bf d1          	movsx  r10d,r9w
 190:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 101.0
- Core cycles: 41.7
- Reference cycles: 30.67
- UOPS_PORT_1: 26.0
- UOPS_PORT_6: 27.7
- UOPS_PORT_0: 25.4
- UOPS_PORT_5: 25.9

⇨ 4 μops that can only use ports {'0', '1', '5', '6'}