VCVTDQ2PD (XMM, M64) - Port Usage

With blocking instructions for ports {'0', '1'}:

Code:

   0:	c5 e9 58 cb          	vaddpd xmm1,xmm2,xmm3
   4:	c5 e9 58 e3          	vaddpd xmm4,xmm2,xmm3
   8:	c5 e9 58 eb          	vaddpd xmm5,xmm2,xmm3
   c:	c5 e9 58 f3          	vaddpd xmm6,xmm2,xmm3
  10:	c5 e9 58 fb          	vaddpd xmm7,xmm2,xmm3
  14:	c5 69 58 c3          	vaddpd xmm8,xmm2,xmm3
  18:	c5 69 58 cb          	vaddpd xmm9,xmm2,xmm3
  1c:	c5 69 58 d3          	vaddpd xmm10,xmm2,xmm3
  20:	c5 69 58 db          	vaddpd xmm11,xmm2,xmm3
  24:	c5 69 58 e3          	vaddpd xmm12,xmm2,xmm3
  28:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM3, [R14]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.57
- Reference cycles: 4.17
- UOPS_PORT_1: 5.5
- UOPS_PORT_0: 5.5

⇨ One μop that can only use ports {'0', '1'}

With blocking instructions for ports {'2', '3'}:

Code:

   0:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
   4:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
   8:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
   c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  10:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
  14:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
  18:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
  1c:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
  20:	41 8b 46 60          	mov    eax,DWORD PTR [r14+0x60]
  24:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
  28:	c4 c1 7a e6 06       	vcvtdq2pd xmm0,QWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.61
- Reference cycles: 4.17
- UOPS_PORT_3: 5.5
- UOPS_PORT_2: 5.5

⇨ One μop that can only use ports {'2', '3'}

With an indexed addressing mode

With blocking instructions for ports {'0', '1'}:

Code:

   0:	c5 e9 58 cb          	vaddpd xmm1,xmm2,xmm3
   4:	c5 e9 58 e3          	vaddpd xmm4,xmm2,xmm3
   8:	c5 e9 58 eb          	vaddpd xmm5,xmm2,xmm3
   c:	c5 e9 58 f3          	vaddpd xmm6,xmm2,xmm3
  10:	c5 e9 58 fb          	vaddpd xmm7,xmm2,xmm3
  14:	c5 69 58 c3          	vaddpd xmm8,xmm2,xmm3
  18:	c5 69 58 cb          	vaddpd xmm9,xmm2,xmm3
  1c:	c5 69 58 d3          	vaddpd xmm10,xmm2,xmm3
  20:	c5 69 58 db          	vaddpd xmm11,xmm2,xmm3
  24:	c5 69 58 e3          	vaddpd xmm12,xmm2,xmm3
  28:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM3, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.59
- Reference cycles: 3.96
- UOPS_PORT_1: 5.49
- UOPS_PORT_0: 5.51

⇨ One μop that can only use ports {'0', '1'}

With blocking instructions for ports {'2', '3'}:

Code:

   0:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
   4:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
   8:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
   c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  10:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
  14:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
  18:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
  1c:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
  20:	41 8b 46 60          	mov    eax,DWORD PTR [r14+0x60]
  24:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
  28:	c4 81 7a e6 04 2e    	vcvtdq2pd xmm0,QWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.63
- Reference cycles: 4.38
- UOPS_PORT_3: 5.5
- UOPS_PORT_2: 5.5

⇨ One μop that can only use ports {'2', '3'}