SQRTSS (XMM, M32) - Port Usage

With blocking instructions for port '0':

Code:

   0:	66 0f 38 de c1       	aesdec xmm0,xmm1
   5:	66 0f 38 de d9       	aesdec xmm3,xmm1
   a:	66 0f 38 de e1       	aesdec xmm4,xmm1
   f:	66 0f 38 de e9       	aesdec xmm5,xmm1
  14:	66 0f 38 de f1       	aesdec xmm6,xmm1
  19:	66 0f 38 de f9       	aesdec xmm7,xmm1
  1e:	66 44 0f 38 de c1    	aesdec xmm8,xmm1
  24:	66 44 0f 38 de c9    	aesdec xmm9,xmm1
  2a:	66 44 0f 38 de d1    	aesdec xmm10,xmm1
  30:	66 44 0f 38 de d9    	aesdec xmm11,xmm1
  36:	66 44 0f 38 de e1    	aesdec xmm12,xmm1
  3c:	66 0f 38 de c1       	aesdec xmm0,xmm1
  41:	66 0f 38 de d9       	aesdec xmm3,xmm1
  46:	66 0f 38 de e1       	aesdec xmm4,xmm1
  4b:	66 0f 38 de e9       	aesdec xmm5,xmm1
  50:	66 0f 38 de f1       	aesdec xmm6,xmm1
  55:	66 0f 38 de f9       	aesdec xmm7,xmm1
  5a:	66 44 0f 38 de c1    	aesdec xmm8,xmm1
  60:	66 44 0f 38 de c9    	aesdec xmm9,xmm1
  66:	66 44 0f 38 de d1    	aesdec xmm10,xmm1
  6c:	66 44 0f 38 de d9    	aesdec xmm11,xmm1
  72:	66 44 0f 38 de e1    	aesdec xmm12,xmm1
  78:	66 0f 38 de c1       	aesdec xmm0,xmm1
  7d:	66 0f 38 de d9       	aesdec xmm3,xmm1
  82:	f3 41 0f 51 16       	sqrtss xmm2,DWORD PTR [r14]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
MOV RAX, 0x3f8000003f800000;
MOV [R14+0], RAX;
MOV [R14+8], RAX

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 26.32
- Reference cycles: 16.26
- UOPS_PORT_0: 24.98

⇨ One μop that can only use port '0'

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
  12:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
  18:	f2 41 0f f0 ae 80 00 	lddqu  xmm5,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 b6 90 00 	lddqu  xmm6,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 be a0 00 	lddqu  xmm7,[r14+0xa0]
  31:	00 00 
  33:	f2 45 0f f0 86 b0 00 	lddqu  xmm8,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 8e c0 00 	lddqu  xmm9,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 96 d0 00 	lddqu  xmm10,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 9e e0 00 	lddqu  xmm11,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 a6 f0 00 	lddqu  xmm12,[r14+0xf0]
  5e:	00 00 
  60:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  66:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  6c:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
  72:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
  78:	f2 41 0f f0 ae 80 00 	lddqu  xmm5,[r14+0x80]
  7f:	00 00 
  81:	f2 41 0f f0 b6 90 00 	lddqu  xmm6,[r14+0x90]
  88:	00 00 
  8a:	f2 41 0f f0 be a0 00 	lddqu  xmm7,[r14+0xa0]
  91:	00 00 
  93:	f2 45 0f f0 86 b0 00 	lddqu  xmm8,[r14+0xb0]
  9a:	00 00 
  9c:	f2 45 0f f0 8e c0 00 	lddqu  xmm9,[r14+0xc0]
  a3:	00 00 
  a5:	f2 45 0f f0 96 d0 00 	lddqu  xmm10,[r14+0xd0]
  ac:	00 00 
  ae:	f2 45 0f f0 9e e0 00 	lddqu  xmm11,[r14+0xe0]
  b5:	00 00 
  b7:	f2 45 0f f0 a6 f0 00 	lddqu  xmm12,[r14+0xf0]
  be:	00 00 
  c0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  c6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  cc:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
  d2:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
  d8:	f2 41 0f f0 ae 80 00 	lddqu  xmm5,[r14+0x80]
  df:	00 00 
  e1:	f2 41 0f f0 b6 90 00 	lddqu  xmm6,[r14+0x90]
  e8:	00 00 
  ea:	f2 41 0f f0 be a0 00 	lddqu  xmm7,[r14+0xa0]
  f1:	00 00 
  f3:	f2 45 0f f0 86 b0 00 	lddqu  xmm8,[r14+0xb0]
  fa:	00 00 
  fc:	f2 45 0f f0 8e c0 00 	lddqu  xmm9,[r14+0xc0]
 103:	00 00 
 105:	f2 45 0f f0 96 d0 00 	lddqu  xmm10,[r14+0xd0]
 10c:	00 00 
 10e:	f2 45 0f f0 9e e0 00 	lddqu  xmm11,[r14+0xe0]
 115:	00 00 
 117:	f2 45 0f f0 a6 f0 00 	lddqu  xmm12,[r14+0xf0]
 11e:	00 00 
 120:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 126:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 12c:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
 132:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
 138:	f2 41 0f f0 ae 80 00 	lddqu  xmm5,[r14+0x80]
 13f:	00 00 
 141:	f2 41 0f f0 b6 90 00 	lddqu  xmm6,[r14+0x90]
 148:	00 00 
 14a:	f2 41 0f f0 be a0 00 	lddqu  xmm7,[r14+0xa0]
 151:	00 00 
 153:	f2 45 0f f0 86 b0 00 	lddqu  xmm8,[r14+0xb0]
 15a:	00 00 
 15c:	f2 45 0f f0 8e c0 00 	lddqu  xmm9,[r14+0xc0]
 163:	00 00 
 165:	f2 45 0f f0 96 d0 00 	lddqu  xmm10,[r14+0xd0]
 16c:	00 00 
 16e:	f2 45 0f f0 9e e0 00 	lddqu  xmm11,[r14+0xe0]
 175:	00 00 
 177:	f2 45 0f f0 a6 f0 00 	lddqu  xmm12,[r14+0xf0]
 17e:	00 00 
 180:	f3 41 0f 51 16       	sqrtss xmm2,DWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV [R14+0], RAX;
MOV [R14+8], RAX

Show nanoBench command
Results:
- Instructions retired: 49.0
- Core cycles: 25.55
- Reference cycles: 15.63
- UOPS_PORT_3: 24.55
- UOPS_PORT_2: 24.55

⇨ One μop that can only use ports {'2', '3'}

With an indexed addressing mode

With blocking instructions for port '0':

Code:

   0:	66 0f 38 de c1       	aesdec xmm0,xmm1
   5:	66 0f 38 de d9       	aesdec xmm3,xmm1
   a:	66 0f 38 de e1       	aesdec xmm4,xmm1
   f:	66 0f 38 de e9       	aesdec xmm5,xmm1
  14:	66 0f 38 de f1       	aesdec xmm6,xmm1
  19:	66 0f 38 de f9       	aesdec xmm7,xmm1
  1e:	66 44 0f 38 de c1    	aesdec xmm8,xmm1
  24:	66 44 0f 38 de c9    	aesdec xmm9,xmm1
  2a:	66 44 0f 38 de d1    	aesdec xmm10,xmm1
  30:	66 44 0f 38 de d9    	aesdec xmm11,xmm1
  36:	66 44 0f 38 de e1    	aesdec xmm12,xmm1
  3c:	66 0f 38 de c1       	aesdec xmm0,xmm1
  41:	66 0f 38 de d9       	aesdec xmm3,xmm1
  46:	66 0f 38 de e1       	aesdec xmm4,xmm1
  4b:	66 0f 38 de e9       	aesdec xmm5,xmm1
  50:	66 0f 38 de f1       	aesdec xmm6,xmm1
  55:	66 0f 38 de f9       	aesdec xmm7,xmm1
  5a:	66 44 0f 38 de c1    	aesdec xmm8,xmm1
  60:	66 44 0f 38 de c9    	aesdec xmm9,xmm1
  66:	66 44 0f 38 de d1    	aesdec xmm10,xmm1
  6c:	66 44 0f 38 de d9    	aesdec xmm11,xmm1
  72:	66 44 0f 38 de e1    	aesdec xmm12,xmm1
  78:	66 0f 38 de c1       	aesdec xmm0,xmm1
  7d:	66 0f 38 de d9       	aesdec xmm3,xmm1
  82:	f3 41 0f 51 16       	sqrtss xmm2,DWORD PTR [r14]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
MOV RAX, 0x3f8000003f800000;
MOV [R14+0], RAX;
MOV [R14+8], RAX

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 26.32
- Reference cycles: 18.29
- UOPS_PORT_0: 25.0

⇨ One μop that can only use port '0'

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
  12:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
  18:	f2 41 0f f0 ae 80 00 	lddqu  xmm5,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 b6 90 00 	lddqu  xmm6,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 be a0 00 	lddqu  xmm7,[r14+0xa0]
  31:	00 00 
  33:	f2 45 0f f0 86 b0 00 	lddqu  xmm8,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 8e c0 00 	lddqu  xmm9,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 96 d0 00 	lddqu  xmm10,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 9e e0 00 	lddqu  xmm11,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 a6 f0 00 	lddqu  xmm12,[r14+0xf0]
  5e:	00 00 
  60:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  66:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  6c:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
  72:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
  78:	f2 41 0f f0 ae 80 00 	lddqu  xmm5,[r14+0x80]
  7f:	00 00 
  81:	f2 41 0f f0 b6 90 00 	lddqu  xmm6,[r14+0x90]
  88:	00 00 
  8a:	f2 41 0f f0 be a0 00 	lddqu  xmm7,[r14+0xa0]
  91:	00 00 
  93:	f2 45 0f f0 86 b0 00 	lddqu  xmm8,[r14+0xb0]
  9a:	00 00 
  9c:	f2 45 0f f0 8e c0 00 	lddqu  xmm9,[r14+0xc0]
  a3:	00 00 
  a5:	f2 45 0f f0 96 d0 00 	lddqu  xmm10,[r14+0xd0]
  ac:	00 00 
  ae:	f2 45 0f f0 9e e0 00 	lddqu  xmm11,[r14+0xe0]
  b5:	00 00 
  b7:	f2 45 0f f0 a6 f0 00 	lddqu  xmm12,[r14+0xf0]
  be:	00 00 
  c0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  c6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  cc:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
  d2:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
  d8:	f2 41 0f f0 ae 80 00 	lddqu  xmm5,[r14+0x80]
  df:	00 00 
  e1:	f2 41 0f f0 b6 90 00 	lddqu  xmm6,[r14+0x90]
  e8:	00 00 
  ea:	f2 41 0f f0 be a0 00 	lddqu  xmm7,[r14+0xa0]
  f1:	00 00 
  f3:	f2 45 0f f0 86 b0 00 	lddqu  xmm8,[r14+0xb0]
  fa:	00 00 
  fc:	f2 45 0f f0 8e c0 00 	lddqu  xmm9,[r14+0xc0]
 103:	00 00 
 105:	f2 45 0f f0 96 d0 00 	lddqu  xmm10,[r14+0xd0]
 10c:	00 00 
 10e:	f2 45 0f f0 9e e0 00 	lddqu  xmm11,[r14+0xe0]
 115:	00 00 
 117:	f2 45 0f f0 a6 f0 00 	lddqu  xmm12,[r14+0xf0]
 11e:	00 00 
 120:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
 126:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
 12c:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
 132:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
 138:	f2 41 0f f0 ae 80 00 	lddqu  xmm5,[r14+0x80]
 13f:	00 00 
 141:	f2 41 0f f0 b6 90 00 	lddqu  xmm6,[r14+0x90]
 148:	00 00 
 14a:	f2 41 0f f0 be a0 00 	lddqu  xmm7,[r14+0xa0]
 151:	00 00 
 153:	f2 45 0f f0 86 b0 00 	lddqu  xmm8,[r14+0xb0]
 15a:	00 00 
 15c:	f2 45 0f f0 8e c0 00 	lddqu  xmm9,[r14+0xc0]
 163:	00 00 
 165:	f2 45 0f f0 96 d0 00 	lddqu  xmm10,[r14+0xd0]
 16c:	00 00 
 16e:	f2 45 0f f0 9e e0 00 	lddqu  xmm11,[r14+0xe0]
 175:	00 00 
 177:	f2 45 0f f0 a6 f0 00 	lddqu  xmm12,[r14+0xf0]
 17e:	00 00 
 180:	f3 41 0f 51 16       	sqrtss xmm2,DWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV [R14+0], RAX;
MOV [R14+8], RAX

Show nanoBench command
Results:
- Instructions retired: 49.0
- Core cycles: 25.55
- Reference cycles: 17.71
- UOPS_PORT_3: 24.5
- UOPS_PORT_2: 24.5

⇨ One μop that can only use ports {'2', '3'}