VBLENDVPD (YMM, YMM, M256, YMM) - Port Usage

With blocking instructions for ports {'0', '1'}:

Code:

   0:	c5 d9 58 dd          	vaddpd xmm3,xmm4,xmm5
   4:	c5 d9 58 f5          	vaddpd xmm6,xmm4,xmm5
   8:	c5 d9 58 fd          	vaddpd xmm7,xmm4,xmm5
   c:	c5 59 58 c5          	vaddpd xmm8,xmm4,xmm5
  10:	c5 59 58 cd          	vaddpd xmm9,xmm4,xmm5
  14:	c5 59 58 d5          	vaddpd xmm10,xmm4,xmm5
  18:	c5 59 58 dd          	vaddpd xmm11,xmm4,xmm5
  1c:	c5 59 58 e5          	vaddpd xmm12,xmm4,xmm5
  20:	c5 d9 58 dd          	vaddpd xmm3,xmm4,xmm5
  24:	c5 d9 58 f5          	vaddpd xmm6,xmm4,xmm5
  28:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM4, [R14];
VMOVUPD XMM5, [R14];
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.12
- Reference cycles: 4.11
- UOPS_PORT_0: 5.01
- UOPS_PORT_1: 5.0

With blocking instructions for ports {'0', '5'}:

Code:

   0:	0f 6f c1             	movq   mm0,mm1
   3:	0f 6f d1             	movq   mm2,mm1
   6:	0f 6f d9             	movq   mm3,mm1
   9:	0f 6f e1             	movq   mm4,mm1
   c:	0f 6f e9             	movq   mm5,mm1
   f:	0f 6f f1             	movq   mm6,mm1
  12:	0f 6f f9             	movq   mm7,mm1
  15:	0f 6f c1             	movq   mm0,mm1
  18:	0f 6f d1             	movq   mm2,mm1
  1b:	0f 6f d9             	movq   mm3,mm1
  1e:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
PXOR MM1, MM1;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.11
- Reference cycles: 3.85
- UOPS_PORT_0: 5.01
- UOPS_PORT_5: 5.0

With blocking instructions for ports {'1', '5'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	41 8d 16             	lea    edx,[r14]
  18:	45 8d 06             	lea    r8d,[r14]
  1b:	45 8d 0e             	lea    r9d,[r14]
  1e:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.07
- Reference cycles: 4.62
- UOPS_PORT_1: 5.0
- UOPS_PORT_5: 5.0

With blocking instructions for ports {'2', '3'}:

Code:

   0:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
   4:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
   8:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
   c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  10:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
  14:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
  18:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
  1c:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
  20:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
  24:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
  28:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.65
- Reference cycles: 4.62
- UOPS_PORT_2: 5.5
- UOPS_PORT_3: 5.5

⇨ One μop that can only use ports {'2', '3'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	c5 d9 55 dd          	vandnpd xmm3,xmm4,xmm5
   4:	c5 d9 55 f5          	vandnpd xmm6,xmm4,xmm5
   8:	c5 d9 55 fd          	vandnpd xmm7,xmm4,xmm5
   c:	c5 59 55 c5          	vandnpd xmm8,xmm4,xmm5
  10:	c5 59 55 cd          	vandnpd xmm9,xmm4,xmm5
  14:	c5 59 55 d5          	vandnpd xmm10,xmm4,xmm5
  18:	c5 59 55 dd          	vandnpd xmm11,xmm4,xmm5
  1c:	c5 59 55 e5          	vandnpd xmm12,xmm4,xmm5
  20:	c5 d9 55 dd          	vandnpd xmm3,xmm4,xmm5
  24:	c5 d9 55 f5          	vandnpd xmm6,xmm4,xmm5
  28:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 4.15
- Reference cycles: 3.08
- UOPS_PORT_0: 3.99
- UOPS_PORT_1: 4.01
- UOPS_PORT_5: 4.0

⇨ 2 μops that can only use ports {'0', '1', '5'}

With an indexed addressing mode

With blocking instructions for ports {'0', '1'}:

Code:

   0:	c5 d9 58 dd          	vaddpd xmm3,xmm4,xmm5
   4:	c5 d9 58 f5          	vaddpd xmm6,xmm4,xmm5
   8:	c5 d9 58 fd          	vaddpd xmm7,xmm4,xmm5
   c:	c5 59 58 c5          	vaddpd xmm8,xmm4,xmm5
  10:	c5 59 58 cd          	vaddpd xmm9,xmm4,xmm5
  14:	c5 59 58 d5          	vaddpd xmm10,xmm4,xmm5
  18:	c5 59 58 dd          	vaddpd xmm11,xmm4,xmm5
  1c:	c5 59 58 e5          	vaddpd xmm12,xmm4,xmm5
  20:	c5 d9 58 dd          	vaddpd xmm3,xmm4,xmm5
  24:	c5 d9 58 f5          	vaddpd xmm6,xmm4,xmm5
  28:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM4, [R14];
VMOVUPD XMM5, [R14];
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.12
- Reference cycles: 4.62
- UOPS_PORT_0: 5.01
- UOPS_PORT_1: 5.0

With blocking instructions for ports {'0', '5'}:

Code:

   0:	0f 6f c1             	movq   mm0,mm1
   3:	0f 6f d1             	movq   mm2,mm1
   6:	0f 6f d9             	movq   mm3,mm1
   9:	0f 6f e1             	movq   mm4,mm1
   c:	0f 6f e9             	movq   mm5,mm1
   f:	0f 6f f1             	movq   mm6,mm1
  12:	0f 6f f9             	movq   mm7,mm1
  15:	0f 6f c1             	movq   mm0,mm1
  18:	0f 6f d1             	movq   mm2,mm1
  1b:	0f 6f d9             	movq   mm3,mm1
  1e:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
PXOR MM1, MM1;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.11
- Reference cycles: 4.62
- UOPS_PORT_0: 5.01
- UOPS_PORT_5: 5.0

With blocking instructions for ports {'1', '5'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	41 8d 16             	lea    edx,[r14]
  18:	45 8d 06             	lea    r8d,[r14]
  1b:	45 8d 0e             	lea    r9d,[r14]
  1e:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.07
- Reference cycles: 4.62
- UOPS_PORT_1: 5.0
- UOPS_PORT_5: 5.0

With blocking instructions for ports {'2', '3'}:

Code:

   0:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
   4:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
   8:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
   c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
  10:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
  14:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
  18:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
  1c:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
  20:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
  24:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
  28:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.65
- Reference cycles: 4.62
- UOPS_PORT_2: 5.51
- UOPS_PORT_3: 5.51

⇨ One μop that can only use ports {'2', '3'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	c5 d9 55 dd          	vandnpd xmm3,xmm4,xmm5
   4:	c5 d9 55 f5          	vandnpd xmm6,xmm4,xmm5
   8:	c5 d9 55 fd          	vandnpd xmm7,xmm4,xmm5
   c:	c5 59 55 c5          	vandnpd xmm8,xmm4,xmm5
  10:	c5 59 55 cd          	vandnpd xmm9,xmm4,xmm5
  14:	c5 59 55 d5          	vandnpd xmm10,xmm4,xmm5
  18:	c5 59 55 dd          	vandnpd xmm11,xmm4,xmm5
  1c:	c5 59 55 e5          	vandnpd xmm12,xmm4,xmm5
  20:	c5 d9 55 dd          	vandnpd xmm3,xmm4,xmm5
  24:	c5 d9 55 f5          	vandnpd xmm6,xmm4,xmm5
  28:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM4, XMM4, XMM4;
VXORPS XMM5, XMM5, XMM5;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 4.15
- Reference cycles: 2.82
- UOPS_PORT_0: 3.99
- UOPS_PORT_1: 4.01
- UOPS_PORT_5: 4.0

⇨ 2 μops that can only use ports {'0', '1', '5'}