PANDN (XMM, M128) - Port Usage

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 4e 40    	lddqu  xmm1,[r14+0x40]
   6:	f2 41 0f f0 56 50    	lddqu  xmm2,[r14+0x50]
   c:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
  12:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
  18:	f2 41 0f f0 ae 80 00 	lddqu  xmm5,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 b6 90 00 	lddqu  xmm6,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 be a0 00 	lddqu  xmm7,[r14+0xa0]
  31:	00 00 
  33:	f2 45 0f f0 86 b0 00 	lddqu  xmm8,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 8e c0 00 	lddqu  xmm9,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 96 d0 00 	lddqu  xmm10,[r14+0xd0]
  4c:	00 00 
  4e:	66 41 0f df 06       	pandn  xmm0,XMMWORD PTR [r14]

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.66
- Reference cycles: 6.0
- UOPS_PORT_2: 5.5
- UOPS_PORT_3: 5.5

⇨ One μop that can only use ports {'2', '3'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	f3 0f d6 c8          	movq2dq xmm1,mm0
   4:	f3 0f d6 d0          	movq2dq xmm2,mm0
   8:	f3 0f d6 d8          	movq2dq xmm3,mm0
   c:	f3 0f d6 e0          	movq2dq xmm4,mm0
  10:	f3 0f d6 e8          	movq2dq xmm5,mm0
  14:	f3 0f d6 f0          	movq2dq xmm6,mm0
  18:	f3 0f d6 f8          	movq2dq xmm7,mm0
  1c:	f3 44 0f d6 c0       	movq2dq xmm8,mm0
  21:	f3 44 0f d6 c8       	movq2dq xmm9,mm0
  26:	f3 44 0f d6 d0       	movq2dq xmm10,mm0
  2b:	66 41 0f df 06       	pandn  xmm0,XMMWORD PTR [r14]

Init:

VZEROALL;
PXOR MM0, MM0;
PXOR XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 3.72
- Reference cycles: 3.93
- UOPS_PORT_1: 3.67
- UOPS_PORT_0: 3.66
- UOPS_PORT_5: 3.66

⇨ One μop that can only use ports {'0', '1', '5'}

With an indexed addressing mode

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 4e 40    	lddqu  xmm1,[r14+0x40]
   6:	f2 41 0f f0 56 50    	lddqu  xmm2,[r14+0x50]
   c:	f2 41 0f f0 5e 60    	lddqu  xmm3,[r14+0x60]
  12:	f2 41 0f f0 66 70    	lddqu  xmm4,[r14+0x70]
  18:	f2 41 0f f0 ae 80 00 	lddqu  xmm5,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 b6 90 00 	lddqu  xmm6,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 be a0 00 	lddqu  xmm7,[r14+0xa0]
  31:	00 00 
  33:	f2 45 0f f0 86 b0 00 	lddqu  xmm8,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 8e c0 00 	lddqu  xmm9,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 96 d0 00 	lddqu  xmm10,[r14+0xd0]
  4c:	00 00 
  4e:	66 43 0f df 04 2e    	pandn  xmm0,XMMWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
PXOR XMM0, XMM0;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.66
- Reference cycles: 6.0
- UOPS_PORT_2: 5.5
- UOPS_PORT_3: 5.5

⇨ One μop that can only use ports {'2', '3'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	f3 0f d6 c8          	movq2dq xmm1,mm0
   4:	f3 0f d6 d0          	movq2dq xmm2,mm0
   8:	f3 0f d6 d8          	movq2dq xmm3,mm0
   c:	f3 0f d6 e0          	movq2dq xmm4,mm0
  10:	f3 0f d6 e8          	movq2dq xmm5,mm0
  14:	f3 0f d6 f0          	movq2dq xmm6,mm0
  18:	f3 0f d6 f8          	movq2dq xmm7,mm0
  1c:	f3 44 0f d6 c0       	movq2dq xmm8,mm0
  21:	f3 44 0f d6 c8       	movq2dq xmm9,mm0
  26:	f3 44 0f d6 d0       	movq2dq xmm10,mm0
  2b:	66 43 0f df 04 2e    	pandn  xmm0,XMMWORD PTR [r14+r13*1]

Init:

VZEROALL;
PXOR MM0, MM0;
PXOR XMM0, XMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 3.72
- Reference cycles: 3.93
- UOPS_PORT_1: 3.67
- UOPS_PORT_0: 3.66
- UOPS_PORT_5: 3.66

⇨ One μop that can only use ports {'0', '1', '5'}