ADD (M32, I32) - Port Usage

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	0f 7e c2             	movd   edx,mm0
  1d:	41 0f 7e c0          	movd   r8d,mm0
  21:	41 0f 7e c1          	movd   r9d,mm0
  25:	41 0f 7e c2          	movd   r10d,mm0
  29:	41 0f 7e c3          	movd   r11d,mm0
  2d:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Init:
```
PXOR MM0, MM0
```
Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 12.04
- Reference cycles: 12.73
- UOPS_PORT_0: 11.99

With blocking instructions for port '1':

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  30:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  35:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 12.07
- Reference cycles: 12.77
- UOPS_PORT_1: 12.01

With blocking instructions for port '4':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  35:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  3c:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 13.1
- Reference cycles: 13.73
- UOPS_PORT_4: 13.0

⇨ One μop that can only use port '4'

With blocking instructions for port '5':

Code:

   0:	66 0f 38 de c1       	aesdec xmm0,xmm1
   5:	66 0f 38 de d1       	aesdec xmm2,xmm1
   a:	66 0f 38 de d9       	aesdec xmm3,xmm1
   f:	66 0f 38 de e1       	aesdec xmm4,xmm1
  14:	66 0f 38 de e9       	aesdec xmm5,xmm1
  19:	66 0f 38 de f1       	aesdec xmm6,xmm1
  1e:	66 0f 38 de f9       	aesdec xmm7,xmm1
  23:	66 44 0f 38 de c1    	aesdec xmm8,xmm1
  29:	66 44 0f 38 de c9    	aesdec xmm9,xmm1
  2f:	66 44 0f 38 de d1    	aesdec xmm10,xmm1
  35:	66 44 0f 38 de d9    	aesdec xmm11,xmm1
  3b:	66 44 0f 38 de e1    	aesdec xmm12,xmm1
  41:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 12.1
- Reference cycles: 12.77
- UOPS_PORT_5: 11.99

With blocking instructions for ports {'0', '1'}:

Code:

   0:	66 0f 59 c1          	mulpd  xmm0,xmm1
   4:	66 0f 59 d1          	mulpd  xmm2,xmm1
   8:	66 0f 59 d9          	mulpd  xmm3,xmm1
   c:	66 0f 59 e1          	mulpd  xmm4,xmm1
  10:	66 0f 59 e9          	mulpd  xmm5,xmm1
  14:	66 0f 59 f1          	mulpd  xmm6,xmm1
  18:	66 0f 59 f9          	mulpd  xmm7,xmm1
  1c:	66 44 0f 59 c1       	mulpd  xmm8,xmm1
  21:	66 44 0f 59 c9       	mulpd  xmm9,xmm1
  26:	66 44 0f 59 d1       	mulpd  xmm10,xmm1
  2b:	66 44 0f 59 d9       	mulpd  xmm11,xmm1
  30:	66 44 0f 59 e1       	mulpd  xmm12,xmm1
  35:	66 0f 59 c1          	mulpd  xmm0,xmm1
  39:	66 0f 59 d1          	mulpd  xmm2,xmm1
  3d:	66 0f 59 d9          	mulpd  xmm3,xmm1
  41:	66 0f 59 e1          	mulpd  xmm4,xmm1
  45:	66 0f 59 e9          	mulpd  xmm5,xmm1
  49:	66 0f 59 f1          	mulpd  xmm6,xmm1
  4d:	66 0f 59 f9          	mulpd  xmm7,xmm1
  51:	66 44 0f 59 c1       	mulpd  xmm8,xmm1
  56:	66 44 0f 59 c9       	mulpd  xmm9,xmm1
  5b:	66 44 0f 59 d1       	mulpd  xmm10,xmm1
  60:	66 44 0f 59 d9       	mulpd  xmm11,xmm1
  65:	66 44 0f 59 e1       	mulpd  xmm12,xmm1
  6a:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 12.17
- Reference cycles: 12.76
- UOPS_PORT_1: 12.02
- UOPS_PORT_0: 11.98

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 c1 c2 00          	rol    dx,0x0
  25:	66 41 c1 c0 00       	rol    r8w,0x0
  2a:	66 41 c1 c1 00       	rol    r9w,0x0
  2f:	66 41 c1 c2 00       	rol    r10w,0x0
  34:	66 41 c1 c3 00       	rol    r11w,0x0
  39:	66 41 c1 c4 00       	rol    r12w,0x0
  3e:	66 c1 c3 00          	rol    bx,0x0
  42:	66 c1 c1 00          	rol    cx,0x0
  46:	66 c1 c2 00          	rol    dx,0x0
  4a:	66 41 c1 c0 00       	rol    r8w,0x0
  4f:	66 41 c1 c1 00       	rol    r9w,0x0
  54:	66 41 c1 c2 00       	rol    r10w,0x0
  59:	66 41 c1 c3 00       	rol    r11w,0x0
  5e:	66 41 c1 c4 00       	rol    r12w,0x0
  63:	66 c1 c3 00          	rol    bx,0x0
  67:	66 c1 c1 00          	rol    cx,0x0
  6b:	66 c1 c2 00          	rol    dx,0x0
  6f:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 12.12
- Reference cycles: 12.68
- UOPS_PORT_6: 12.0
- UOPS_PORT_0: 11.98

With blocking instructions for ports {'1', '5'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	41 8d 16             	lea    edx,[r14]
  18:	45 8d 06             	lea    r8d,[r14]
  1b:	45 8d 0e             	lea    r9d,[r14]
  1e:	45 8d 16             	lea    r10d,[r14]
  21:	45 8d 1e             	lea    r11d,[r14]
  24:	45 8d 26             	lea    r12d,[r14]
  27:	41 8d 1e             	lea    ebx,[r14]
  2a:	41 8d 0e             	lea    ecx,[r14]
  2d:	41 8d 16             	lea    edx,[r14]
  30:	45 8d 06             	lea    r8d,[r14]
  33:	45 8d 0e             	lea    r9d,[r14]
  36:	45 8d 16             	lea    r10d,[r14]
  39:	45 8d 1e             	lea    r11d,[r14]
  3c:	45 8d 26             	lea    r12d,[r14]
  3f:	41 8d 1e             	lea    ebx,[r14]
  42:	41 8d 0e             	lea    ecx,[r14]
  45:	41 8d 16             	lea    edx,[r14]
  48:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 12.12
- Reference cycles: 12.68
- UOPS_PORT_1: 12.02
- UOPS_PORT_5: 11.98

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  81:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  88:	00 00 
  8a:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  91:	00 00 
  93:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  9a:	00 00 
  9c:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  a3:	00 00 
  a5:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  ac:	00 00 
  ae:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  b5:	00 00 
  b7:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  be:	00 00 
  c0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 12.8
- Reference cycles: 13.5
- UOPS_PORT_2: 12.5
- UOPS_PORT_3: 12.5

⇨ One μop that can only use ports {'2', '3'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	f3 0f d6 c0          	movq2dq xmm0,mm0
   4:	f3 0f d6 c8          	movq2dq xmm1,mm0
   8:	f3 0f d6 d0          	movq2dq xmm2,mm0
   c:	f3 0f d6 d8          	movq2dq xmm3,mm0
  10:	f3 0f d6 e0          	movq2dq xmm4,mm0
  14:	f3 0f d6 e8          	movq2dq xmm5,mm0
  18:	f3 0f d6 f0          	movq2dq xmm6,mm0
  1c:	f3 0f d6 f8          	movq2dq xmm7,mm0
  20:	f3 44 0f d6 c0       	movq2dq xmm8,mm0
  25:	f3 44 0f d6 c8       	movq2dq xmm9,mm0
  2a:	f3 44 0f d6 d0       	movq2dq xmm10,mm0
  2f:	f3 44 0f d6 d8       	movq2dq xmm11,mm0
  34:	f3 44 0f d6 e0       	movq2dq xmm12,mm0
  39:	f3 0f d6 c0          	movq2dq xmm0,mm0
  3d:	f3 0f d6 c8          	movq2dq xmm1,mm0
  41:	f3 0f d6 d0          	movq2dq xmm2,mm0
  45:	f3 0f d6 d8          	movq2dq xmm3,mm0
  49:	f3 0f d6 e0          	movq2dq xmm4,mm0
  4d:	f3 0f d6 e8          	movq2dq xmm5,mm0
  51:	f3 0f d6 f0          	movq2dq xmm6,mm0
  55:	f3 0f d6 f8          	movq2dq xmm7,mm0
  59:	f3 44 0f d6 c0       	movq2dq xmm8,mm0
  5e:	f3 44 0f d6 c8       	movq2dq xmm9,mm0
  63:	f3 44 0f d6 d0       	movq2dq xmm10,mm0
  68:	f3 44 0f d6 d8       	movq2dq xmm11,mm0
  6d:	f3 44 0f d6 e0       	movq2dq xmm12,mm0
  72:	f3 0f d6 c0          	movq2dq xmm0,mm0
  76:	f3 0f d6 c8          	movq2dq xmm1,mm0
  7a:	f3 0f d6 d0          	movq2dq xmm2,mm0
  7e:	f3 0f d6 d8          	movq2dq xmm3,mm0
  82:	f3 0f d6 e0          	movq2dq xmm4,mm0
  86:	f3 0f d6 e8          	movq2dq xmm5,mm0
  8a:	f3 0f d6 f0          	movq2dq xmm6,mm0
  8e:	f3 0f d6 f8          	movq2dq xmm7,mm0
  92:	f3 44 0f d6 c0       	movq2dq xmm8,mm0
  97:	f3 44 0f d6 c8       	movq2dq xmm9,mm0
  9c:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Init:
```
VZEROALL;
PXOR MM0, MM0
```
Show nanoBench command
Results:
- Instructions retired: 37.0
- Core cycles: 12.22
- Reference cycles: 13.33
- UOPS_PORT_1: 12.0
- UOPS_PORT_0: 12.04
- UOPS_PORT_5: 12.0

With blocking instructions for ports {'2', '3', '7'}:

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  35:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  3c:	4d 89 86 a0 00 00 00 	mov    QWORD PTR [r14+0xa0],r8
  43:	4d 89 86 a8 00 00 00 	mov    QWORD PTR [r14+0xa8],r8
  4a:	4d 89 86 b0 00 00 00 	mov    QWORD PTR [r14+0xb0],r8
  51:	4d 89 86 b8 00 00 00 	mov    QWORD PTR [r14+0xb8],r8
  58:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
  5c:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
  60:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
  64:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  68:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  6c:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  70:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  74:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  78:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  7f:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  86:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  8d:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  94:	4d 89 86 a0 00 00 00 	mov    QWORD PTR [r14+0xa0],r8
  9b:	4d 89 86 a8 00 00 00 	mov    QWORD PTR [r14+0xa8],r8
  a2:	4d 89 86 b0 00 00 00 	mov    QWORD PTR [r14+0xb0],r8
  a9:	4d 89 86 b8 00 00 00 	mov    QWORD PTR [r14+0xb8],r8
  b0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
  b4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
  b8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
  bc:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  c0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 37.0
- Core cycles: 37.3
- Reference cycles: 39.26
- UOPS_PORT_7: 12.74
- UOPS_PORT_2: 12.43
- UOPS_PORT_3: 12.83

⇨ One μop that can only use ports {'2', '3', '7'}

With blocking instructions for ports {'0', '1', '5', '6'}:

Code:

   0:	45 0f bf c1          	movsx  r8d,r9w
   4:	45 0f bf d1          	movsx  r10d,r9w
   8:	45 0f bf d9          	movsx  r11d,r9w
   c:	45 0f bf e1          	movsx  r12d,r9w
  10:	41 0f bf d9          	movsx  ebx,r9w
  14:	41 0f bf c9          	movsx  ecx,r9w
  18:	41 0f bf d1          	movsx  edx,r9w
  1c:	45 0f bf c1          	movsx  r8d,r9w
  20:	45 0f bf d1          	movsx  r10d,r9w
  24:	45 0f bf d9          	movsx  r11d,r9w
  28:	45 0f bf e1          	movsx  r12d,r9w
  2c:	41 0f bf d9          	movsx  ebx,r9w
  30:	41 0f bf c9          	movsx  ecx,r9w
  34:	41 0f bf d1          	movsx  edx,r9w
  38:	45 0f bf c1          	movsx  r8d,r9w
  3c:	45 0f bf d1          	movsx  r10d,r9w
  40:	45 0f bf d9          	movsx  r11d,r9w
  44:	45 0f bf e1          	movsx  r12d,r9w
  48:	41 0f bf d9          	movsx  ebx,r9w
  4c:	41 0f bf c9          	movsx  ecx,r9w
  50:	41 0f bf d1          	movsx  edx,r9w
  54:	45 0f bf c1          	movsx  r8d,r9w
  58:	45 0f bf d1          	movsx  r10d,r9w
  5c:	45 0f bf d9          	movsx  r11d,r9w
  60:	45 0f bf e1          	movsx  r12d,r9w
  64:	41 0f bf d9          	movsx  ebx,r9w
  68:	41 0f bf c9          	movsx  ecx,r9w
  6c:	41 0f bf d1          	movsx  edx,r9w
  70:	45 0f bf c1          	movsx  r8d,r9w
  74:	45 0f bf d1          	movsx  r10d,r9w
  78:	45 0f bf d9          	movsx  r11d,r9w
  7c:	45 0f bf e1          	movsx  r12d,r9w
  80:	41 0f bf d9          	movsx  ebx,r9w
  84:	41 0f bf c9          	movsx  ecx,r9w
  88:	41 0f bf d1          	movsx  edx,r9w
  8c:	45 0f bf c1          	movsx  r8d,r9w
  90:	45 0f bf d1          	movsx  r10d,r9w
  94:	45 0f bf d9          	movsx  r11d,r9w
  98:	45 0f bf e1          	movsx  r12d,r9w
  9c:	41 0f bf d9          	movsx  ebx,r9w
  a0:	41 0f bf c9          	movsx  ecx,r9w
  a4:	41 0f bf d1          	movsx  edx,r9w
  a8:	45 0f bf c1          	movsx  r8d,r9w
  ac:	45 0f bf d1          	movsx  r10d,r9w
  b0:	45 0f bf d9          	movsx  r11d,r9w
  b4:	45 0f bf e1          	movsx  r12d,r9w
  b8:	41 0f bf d9          	movsx  ebx,r9w
  bc:	41 0f bf c9          	movsx  ecx,r9w
  c0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 49.0
- Core cycles: 13.33
- Reference cycles: 14.0
- UOPS_PORT_1: 12.45
- UOPS_PORT_0: 11.7
- UOPS_PORT_5: 12.3
- UOPS_PORT_6: 12.55

⇨ One μop that can only use ports {'0', '1', '5', '6'}

With an indexed addressing mode

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	0f 7e c2             	movd   edx,mm0
  1d:	41 0f 7e c0          	movd   r8d,mm0
  21:	41 0f 7e c1          	movd   r9d,mm0
  25:	41 0f 7e c2          	movd   r10d,mm0
  29:	41 0f 7e c3          	movd   r11d,mm0
  2d:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  34:	01

Init:
```
PXOR MM0, MM0;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 12.06
- Reference cycles: 12.77
- UOPS_PORT_0: 12.0

With blocking instructions for port '1':

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  30:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  35:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  3c:	01

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 12.09
- Reference cycles: 12.73
- UOPS_PORT_1: 12.0

With blocking instructions for port '4':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  35:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  3c:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  43:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 13.11
- Reference cycles: 13.73
- UOPS_PORT_4: 13.0

⇨ One μop that can only use port '4'

With blocking instructions for port '5':

Code:

   0:	66 0f 38 de c1       	aesdec xmm0,xmm1
   5:	66 0f 38 de d1       	aesdec xmm2,xmm1
   a:	66 0f 38 de d9       	aesdec xmm3,xmm1
   f:	66 0f 38 de e1       	aesdec xmm4,xmm1
  14:	66 0f 38 de e9       	aesdec xmm5,xmm1
  19:	66 0f 38 de f1       	aesdec xmm6,xmm1
  1e:	66 0f 38 de f9       	aesdec xmm7,xmm1
  23:	66 44 0f 38 de c1    	aesdec xmm8,xmm1
  29:	66 44 0f 38 de c9    	aesdec xmm9,xmm1
  2f:	66 44 0f 38 de d1    	aesdec xmm10,xmm1
  35:	66 44 0f 38 de d9    	aesdec xmm11,xmm1
  3b:	66 44 0f 38 de e1    	aesdec xmm12,xmm1
  41:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  48:	01

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 12.13
- Reference cycles: 12.77
- UOPS_PORT_5: 11.99

With blocking instructions for ports {'0', '1'}:

Code:

   0:	66 0f 59 c1          	mulpd  xmm0,xmm1
   4:	66 0f 59 d1          	mulpd  xmm2,xmm1
   8:	66 0f 59 d9          	mulpd  xmm3,xmm1
   c:	66 0f 59 e1          	mulpd  xmm4,xmm1
  10:	66 0f 59 e9          	mulpd  xmm5,xmm1
  14:	66 0f 59 f1          	mulpd  xmm6,xmm1
  18:	66 0f 59 f9          	mulpd  xmm7,xmm1
  1c:	66 44 0f 59 c1       	mulpd  xmm8,xmm1
  21:	66 44 0f 59 c9       	mulpd  xmm9,xmm1
  26:	66 44 0f 59 d1       	mulpd  xmm10,xmm1
  2b:	66 44 0f 59 d9       	mulpd  xmm11,xmm1
  30:	66 44 0f 59 e1       	mulpd  xmm12,xmm1
  35:	66 0f 59 c1          	mulpd  xmm0,xmm1
  39:	66 0f 59 d1          	mulpd  xmm2,xmm1
  3d:	66 0f 59 d9          	mulpd  xmm3,xmm1
  41:	66 0f 59 e1          	mulpd  xmm4,xmm1
  45:	66 0f 59 e9          	mulpd  xmm5,xmm1
  49:	66 0f 59 f1          	mulpd  xmm6,xmm1
  4d:	66 0f 59 f9          	mulpd  xmm7,xmm1
  51:	66 44 0f 59 c1       	mulpd  xmm8,xmm1
  56:	66 44 0f 59 c9       	mulpd  xmm9,xmm1
  5b:	66 44 0f 59 d1       	mulpd  xmm10,xmm1
  60:	66 44 0f 59 d9       	mulpd  xmm11,xmm1
  65:	66 44 0f 59 e1       	mulpd  xmm12,xmm1
  6a:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  71:	01

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 12.21
- Reference cycles: 12.93
- UOPS_PORT_1: 12.0
- UOPS_PORT_0: 12.0

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 c1 c2 00          	rol    dx,0x0
  25:	66 41 c1 c0 00       	rol    r8w,0x0
  2a:	66 41 c1 c1 00       	rol    r9w,0x0
  2f:	66 41 c1 c2 00       	rol    r10w,0x0
  34:	66 41 c1 c3 00       	rol    r11w,0x0
  39:	66 41 c1 c4 00       	rol    r12w,0x0
  3e:	66 c1 c3 00          	rol    bx,0x0
  42:	66 c1 c1 00          	rol    cx,0x0
  46:	66 c1 c2 00          	rol    dx,0x0
  4a:	66 41 c1 c0 00       	rol    r8w,0x0
  4f:	66 41 c1 c1 00       	rol    r9w,0x0
  54:	66 41 c1 c2 00       	rol    r10w,0x0
  59:	66 41 c1 c3 00       	rol    r11w,0x0
  5e:	66 41 c1 c4 00       	rol    r12w,0x0
  63:	66 c1 c3 00          	rol    bx,0x0
  67:	66 c1 c1 00          	rol    cx,0x0
  6b:	66 c1 c2 00          	rol    dx,0x0
  6f:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  76:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 12.15
- Reference cycles: 12.76
- UOPS_PORT_6: 11.98
- UOPS_PORT_0: 12.0

With blocking instructions for ports {'1', '5'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	41 8d 16             	lea    edx,[r14]
  18:	45 8d 06             	lea    r8d,[r14]
  1b:	45 8d 0e             	lea    r9d,[r14]
  1e:	45 8d 16             	lea    r10d,[r14]
  21:	45 8d 1e             	lea    r11d,[r14]
  24:	45 8d 26             	lea    r12d,[r14]
  27:	41 8d 1e             	lea    ebx,[r14]
  2a:	41 8d 0e             	lea    ecx,[r14]
  2d:	41 8d 16             	lea    edx,[r14]
  30:	45 8d 06             	lea    r8d,[r14]
  33:	45 8d 0e             	lea    r9d,[r14]
  36:	45 8d 16             	lea    r10d,[r14]
  39:	45 8d 1e             	lea    r11d,[r14]
  3c:	45 8d 26             	lea    r12d,[r14]
  3f:	41 8d 1e             	lea    ebx,[r14]
  42:	41 8d 0e             	lea    ecx,[r14]
  45:	41 8d 16             	lea    edx,[r14]
  48:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  4f:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 12.15
- Reference cycles: 12.68
- UOPS_PORT_1: 12.0
- UOPS_PORT_5: 11.98

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  81:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  88:	00 00 
  8a:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  91:	00 00 
  93:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  9a:	00 00 
  9c:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  a3:	00 00 
  a5:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  ac:	00 00 
  ae:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  b5:	00 00 
  b7:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  be:	00 00 
  c0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  c7:	01

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 13.27
- Reference cycles: 14.06
- UOPS_PORT_2: 13.01
- UOPS_PORT_3: 12.99

⇨ 2 μops that can only use ports {'2', '3'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	f3 0f d6 c0          	movq2dq xmm0,mm0
   4:	f3 0f d6 c8          	movq2dq xmm1,mm0
   8:	f3 0f d6 d0          	movq2dq xmm2,mm0
   c:	f3 0f d6 d8          	movq2dq xmm3,mm0
  10:	f3 0f d6 e0          	movq2dq xmm4,mm0
  14:	f3 0f d6 e8          	movq2dq xmm5,mm0
  18:	f3 0f d6 f0          	movq2dq xmm6,mm0
  1c:	f3 0f d6 f8          	movq2dq xmm7,mm0
  20:	f3 44 0f d6 c0       	movq2dq xmm8,mm0
  25:	f3 44 0f d6 c8       	movq2dq xmm9,mm0
  2a:	f3 44 0f d6 d0       	movq2dq xmm10,mm0
  2f:	f3 44 0f d6 d8       	movq2dq xmm11,mm0
  34:	f3 44 0f d6 e0       	movq2dq xmm12,mm0
  39:	f3 0f d6 c0          	movq2dq xmm0,mm0
  3d:	f3 0f d6 c8          	movq2dq xmm1,mm0
  41:	f3 0f d6 d0          	movq2dq xmm2,mm0
  45:	f3 0f d6 d8          	movq2dq xmm3,mm0
  49:	f3 0f d6 e0          	movq2dq xmm4,mm0
  4d:	f3 0f d6 e8          	movq2dq xmm5,mm0
  51:	f3 0f d6 f0          	movq2dq xmm6,mm0
  55:	f3 0f d6 f8          	movq2dq xmm7,mm0
  59:	f3 44 0f d6 c0       	movq2dq xmm8,mm0
  5e:	f3 44 0f d6 c8       	movq2dq xmm9,mm0
  63:	f3 44 0f d6 d0       	movq2dq xmm10,mm0
  68:	f3 44 0f d6 d8       	movq2dq xmm11,mm0
  6d:	f3 44 0f d6 e0       	movq2dq xmm12,mm0
  72:	f3 0f d6 c0          	movq2dq xmm0,mm0
  76:	f3 0f d6 c8          	movq2dq xmm1,mm0
  7a:	f3 0f d6 d0          	movq2dq xmm2,mm0
  7e:	f3 0f d6 d8          	movq2dq xmm3,mm0
  82:	f3 0f d6 e0          	movq2dq xmm4,mm0
  86:	f3 0f d6 e8          	movq2dq xmm5,mm0
  8a:	f3 0f d6 f0          	movq2dq xmm6,mm0
  8e:	f3 0f d6 f8          	movq2dq xmm7,mm0
  92:	f3 44 0f d6 c0       	movq2dq xmm8,mm0
  97:	f3 44 0f d6 c8       	movq2dq xmm9,mm0
  9c:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  a3:	01

Init:
```
VZEROALL;
PXOR MM0, MM0;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 37.0
- Core cycles: 12.26
- Reference cycles: 13.09
- UOPS_PORT_1: 12.0
- UOPS_PORT_0: 12.04
- UOPS_PORT_5: 11.96

With blocking instructions for ports {'0', '1', '5', '6'}:

Code:

   0:	45 0f bf c1          	movsx  r8d,r9w
   4:	45 0f bf d1          	movsx  r10d,r9w
   8:	45 0f bf d9          	movsx  r11d,r9w
   c:	45 0f bf e1          	movsx  r12d,r9w
  10:	41 0f bf d9          	movsx  ebx,r9w
  14:	41 0f bf c9          	movsx  ecx,r9w
  18:	41 0f bf d1          	movsx  edx,r9w
  1c:	45 0f bf c1          	movsx  r8d,r9w
  20:	45 0f bf d1          	movsx  r10d,r9w
  24:	45 0f bf d9          	movsx  r11d,r9w
  28:	45 0f bf e1          	movsx  r12d,r9w
  2c:	41 0f bf d9          	movsx  ebx,r9w
  30:	41 0f bf c9          	movsx  ecx,r9w
  34:	41 0f bf d1          	movsx  edx,r9w
  38:	45 0f bf c1          	movsx  r8d,r9w
  3c:	45 0f bf d1          	movsx  r10d,r9w
  40:	45 0f bf d9          	movsx  r11d,r9w
  44:	45 0f bf e1          	movsx  r12d,r9w
  48:	41 0f bf d9          	movsx  ebx,r9w
  4c:	41 0f bf c9          	movsx  ecx,r9w
  50:	41 0f bf d1          	movsx  edx,r9w
  54:	45 0f bf c1          	movsx  r8d,r9w
  58:	45 0f bf d1          	movsx  r10d,r9w
  5c:	45 0f bf d9          	movsx  r11d,r9w
  60:	45 0f bf e1          	movsx  r12d,r9w
  64:	41 0f bf d9          	movsx  ebx,r9w
  68:	41 0f bf c9          	movsx  ecx,r9w
  6c:	41 0f bf d1          	movsx  edx,r9w
  70:	45 0f bf c1          	movsx  r8d,r9w
  74:	45 0f bf d1          	movsx  r10d,r9w
  78:	45 0f bf d9          	movsx  r11d,r9w
  7c:	45 0f bf e1          	movsx  r12d,r9w
  80:	41 0f bf d9          	movsx  ebx,r9w
  84:	41 0f bf c9          	movsx  ecx,r9w
  88:	41 0f bf d1          	movsx  edx,r9w
  8c:	45 0f bf c1          	movsx  r8d,r9w
  90:	45 0f bf d1          	movsx  r10d,r9w
  94:	45 0f bf d9          	movsx  r11d,r9w
  98:	45 0f bf e1          	movsx  r12d,r9w
  9c:	41 0f bf d9          	movsx  ebx,r9w
  a0:	41 0f bf c9          	movsx  ecx,r9w
  a4:	41 0f bf d1          	movsx  edx,r9w
  a8:	45 0f bf c1          	movsx  r8d,r9w
  ac:	45 0f bf d1          	movsx  r10d,r9w
  b0:	45 0f bf d9          	movsx  r11d,r9w
  b4:	45 0f bf e1          	movsx  r12d,r9w
  b8:	41 0f bf d9          	movsx  ebx,r9w
  bc:	41 0f bf c9          	movsx  ecx,r9w
  c0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  c7:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 49.0
- Core cycles: 13.58
- Reference cycles: 14.33
- UOPS_PORT_1: 12.0
- UOPS_PORT_0: 11.9
- UOPS_PORT_5: 12.9
- UOPS_PORT_6: 12.2

⇨ One μop that can only use ports {'0', '1', '5', '6'}