STMXCSR (M32) - Port Usage

With lfence (to avoid incorrect counts due to replays)

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop
   b:	90                   	nop
   c:	90                   	nop
   d:	90                   	nop
   e:	0f ae e8             	lfence

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 26.83
- Reference cycles: 18.69
- UOPS_DISPATCHED.INT_EU_ALL: 2.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.LD: 0.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0

No uops

With an indexed addressing mode

With lfence (to avoid incorrect counts due to replays)

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop
   b:	90                   	nop
   c:	90                   	nop
   d:	90                   	nop
   e:	90                   	nop
   f:	0f ae e8             	lfence

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 26.66
- Reference cycles: 18.52
- UOPS_DISPATCHED.INT_EU_ALL: 2.01
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.LD: 0.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 1.0

No uops