SQRTSS (XMM, M32) - Port Usage

With lfence (to avoid incorrect counts due to replays)

Code:

   0:	f3 41 0f 51 16       	sqrtss xmm2,DWORD PTR [r14]
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop
   b:	90                   	nop
   c:	90                   	nop
   d:	90                   	nop
   e:	90                   	nop
   f:	0f ae e8             	lfence

Init:

VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV [R14+0], RAX;
MOV [R14+8], RAX

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 29.0
- Reference cycles: 20.71
- UOPS_DISPATCHED.INT_EU_ALL: 1.0
- UOPS_DISPATCHED.ALU: 0.99
- UOPS_DISPATCHED.LD: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 0.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 0.0

Port usage: 1*p10

With an indexed addressing mode

With lfence (to avoid incorrect counts due to replays)

Code:

   0:	f3 41 0f 51 16       	sqrtss xmm2,DWORD PTR [r14]
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop
   b:	90                   	nop
   c:	90                   	nop
   d:	90                   	nop
   e:	90                   	nop
   f:	0f ae e8             	lfence

Init:

VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV [R14+0], RAX;
MOV [R14+8], RAX

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 29.0
- Reference cycles: 20.54
- UOPS_DISPATCHED.INT_EU_ALL: 1.0
- UOPS_DISPATCHED.ALU: 1.01
- UOPS_DISPATCHED.LD: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 0.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 0.0

Port usage: 1*p10