DIV (M64) - Port Usage

With lfence (to avoid incorrect counts due to replays)

Code:

   0:	48 c7 c0 00 00 00 00 	mov    rax,0x0
   7:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
   e:	49 f7 36             	div    QWORD PTR [r14]
  11:	90                   	nop
  12:	90                   	nop
  13:	90                   	nop
  14:	90                   	nop
  15:	90                   	nop
  16:	90                   	nop
  17:	90                   	nop
  18:	90                   	nop
  19:	90                   	nop
  1a:	90                   	nop
  1b:	0f ae e8             	lfence

Init:

MOV qword ptr [R14], 1;
MOV RAX, 0;
MOV RDX, 0

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 35.49
- Reference cycles: 24.91
- UOPS_DISPATCHED.INT_EU_ALL: 7.0
- UOPS_DISPATCHED.ALU: 4.0
- UOPS_DISPATCHED.LD: 1.0
- UOPS_DISPATCHED.SLOW: 2.0
- UOPS_DISPATCHED.STD: 0.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 0.0

Code:

   0:	48 c7 c0 00 00 00 00 	mov    rax,0x0
   7:	48 c7 c2 00 00 00 00 	mov    rdx,0x0

Init:

MOV qword ptr [R14], 1;
MOV RAX, 0;
MOV RDX, 0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.33
- Reference cycles: 0.34
- UOPS_DISPATCHED.INT_EU_ALL: 2.0
- UOPS_DISPATCHED.ALU: 2.0
- UOPS_DISPATCHED.LD: 0.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 0.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 0.0

No uops

With an indexed addressing mode

With lfence (to avoid incorrect counts due to replays)

Code:

   0:	48 c7 c0 00 00 00 00 	mov    rax,0x0
   7:	48 c7 c2 00 00 00 00 	mov    rdx,0x0
   e:	49 f7 36             	div    QWORD PTR [r14]
  11:	90                   	nop
  12:	90                   	nop
  13:	90                   	nop
  14:	90                   	nop
  15:	90                   	nop
  16:	90                   	nop
  17:	90                   	nop
  18:	90                   	nop
  19:	90                   	nop
  1a:	90                   	nop
  1b:	0f ae e8             	lfence

Init:

MOV qword ptr [R14], 1;
MOV RAX, 0;
MOV RDX, 0

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 35.51
- Reference cycles: 25.08
- UOPS_DISPATCHED.INT_EU_ALL: 7.0
- UOPS_DISPATCHED.ALU: 4.0
- UOPS_DISPATCHED.LD: 1.0
- UOPS_DISPATCHED.SLOW: 2.0
- UOPS_DISPATCHED.STD: 0.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 0.0

Code:

   0:	48 c7 c0 00 00 00 00 	mov    rax,0x0
   7:	48 c7 c2 00 00 00 00 	mov    rdx,0x0

Init:

MOV qword ptr [R14], 1;
MOV RAX, 0;
MOV RDX, 0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 0.32
- Reference cycles: 0.51
- UOPS_DISPATCHED.INT_EU_ALL: 2.0
- UOPS_DISPATCHED.ALU: 2.0
- UOPS_DISPATCHED.LD: 0.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 0.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 0.0

No uops