ADDSD (XMM, M64) - Port Usage

With lfence (to avoid incorrect counts due to replays)

• Code:

     0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
     5:	90                   	nop
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
     a:	90                   	nop
     b:	90                   	nop
     c:	90                   	nop
     d:	90                   	nop
     e:	90                   	nop
     f:	0f ae e8             	lfence
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14]

• Show nanoBench command
• Results:
  • Instructions retired: 12.0
  • Core cycles: 22.0
  • Reference cycles: 15.49
  • UOPS_DISPATCHED.INT_EU_ALL: 1.0
  • UOPS_DISPATCHED.ALU: 1.0
  • UOPS_DISPATCHED.LD: 1.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 0.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0

With an indexed addressing mode

With lfence (to avoid incorrect counts due to replays)

• Code:

     0:	f2 43 0f 58 04 2e    	addsd  xmm0,QWORD PTR [r14+r13*1]
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
     a:	90                   	nop
     b:	90                   	nop
     c:	90                   	nop
     d:	90                   	nop
     e:	90                   	nop
     f:	90                   	nop
    10:	0f ae e8             	lfence
  

• Init:

  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOVUPD XMM0, [R14];
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 12.0
  • Core cycles: 22.0
  • Reference cycles: 15.66
  • UOPS_DISPATCHED.INT_EU_ALL: 0.99
  • UOPS_DISPATCHED.ALU: 1.01
  • UOPS_DISPATCHED.LD: 1.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 0.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0