VBLENDVPD (YMM, YMM, M256, YMM) - Port Usage

With blocking instructions for port '0':

• Code:

     0:	41 0f 7e c0          	movd   r8d,mm0
     4:	41 0f 7e c1          	movd   r9d,mm0
     8:	41 0f 7e c2          	movd   r10d,mm0
     c:	41 0f 7e c3          	movd   r11d,mm0
    10:	41 0f 7e c4          	movd   r12d,mm0
    14:	0f 7e c3             	movd   ebx,mm0
    17:	0f 7e c1             	movd   ecx,mm0
    1a:	0f 7e c2             	movd   edx,mm0
    1d:	41 0f 7e c0          	movd   r8d,mm0
    21:	41 0f 7e c1          	movd   r9d,mm0
    25:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  PXOR MM0, MM0;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2

• Show nanoBench command
• Results:
  • Instructions retired: 11.0
  • Core cycles: 10.02
  • Reference cycles: 7.52
  • UOPS_PORT_0: 10.0

With blocking instructions for port '1':

• Code:

     0:	44 8d 05 80 00 00 00 	lea    r8d,[rip+0x80]        # 0x87
     7:	44 8d 0d 80 00 00 00 	lea    r9d,[rip+0x80]        # 0x8e
     e:	44 8d 15 80 00 00 00 	lea    r10d,[rip+0x80]        # 0x95
    15:	44 8d 1d 80 00 00 00 	lea    r11d,[rip+0x80]        # 0x9c
    1c:	44 8d 25 80 00 00 00 	lea    r12d,[rip+0x80]        # 0xa3
    23:	8d 1d 80 00 00 00    	lea    ebx,[rip+0x80]        # 0xa9
    29:	8d 0d 80 00 00 00    	lea    ecx,[rip+0x80]        # 0xaf
    2f:	8d 15 80 00 00 00    	lea    edx,[rip+0x80]        # 0xb5
    35:	44 8d 05 80 00 00 00 	lea    r8d,[rip+0x80]        # 0xbc
    3c:	44 8d 0d 80 00 00 00 	lea    r9d,[rip+0x80]        # 0xc3
    43:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2

• Show nanoBench command
• Results:
  • Instructions retired: 11.0
  • Core cycles: 9.99
  • Reference cycles: 7.36
  • UOPS_PORT_1: 10.0

With blocking instructions for port '23A':

• Code:

     0:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
     4:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
     8:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
     c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
    10:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
    14:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
    18:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
    1c:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
    20:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
    24:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
    28:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
    2c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
    30:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2

• Show nanoBench command
• Results:
  • Instructions retired: 13.0
  • Core cycles: 4.47
  • Reference cycles: 3.47
  • UOPS_PORT_23A: 13.0

With blocking instructions for port '5':

• Code:

     0:	41 0f 6e c0          	movd   mm0,r8d
     4:	41 0f 6e c8          	movd   mm1,r8d
     8:	41 0f 6e d0          	movd   mm2,r8d
     c:	41 0f 6e d8          	movd   mm3,r8d
    10:	41 0f 6e e0          	movd   mm4,r8d
    14:	41 0f 6e e8          	movd   mm5,r8d
    18:	41 0f 6e f0          	movd   mm6,r8d
    1c:	41 0f 6e f8          	movd   mm7,r8d
    20:	41 0f 6e c0          	movd   mm0,r8d
    24:	41 0f 6e c8          	movd   mm1,r8d
    28:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2

• Show nanoBench command
• Results:
  • Instructions retired: 11.0
  • Core cycles: 10.03
  • Reference cycles: 7.52
  • UOPS_PORT_5B: 10.0
  • UOPS_PORT_5B>=2: 0.0

With blocking instructions for ports {'0', '1'}:

• Code:

     0:	c4 e2 59 de dd       	vaesdec xmm3,xmm4,xmm5
     5:	c4 e2 59 de f5       	vaesdec xmm6,xmm4,xmm5
     a:	c4 e2 59 de fd       	vaesdec xmm7,xmm4,xmm5
     f:	c4 62 59 de c5       	vaesdec xmm8,xmm4,xmm5
    14:	c4 62 59 de cd       	vaesdec xmm9,xmm4,xmm5
    19:	c4 62 59 de d5       	vaesdec xmm10,xmm4,xmm5
    1e:	c4 62 59 de dd       	vaesdec xmm11,xmm4,xmm5
    23:	c4 62 59 de e5       	vaesdec xmm12,xmm4,xmm5
    28:	c4 e2 59 de dd       	vaesdec xmm3,xmm4,xmm5
    2d:	c4 e2 59 de f5       	vaesdec xmm6,xmm4,xmm5
    32:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM4, XMM4, XMM4;
  VXORPS XMM5, XMM5, XMM5;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2

• Show nanoBench command
• Results:
  • Instructions retired: 11.0
  • Core cycles: 5.08
  • Reference cycles: 3.84
  • UOPS_PORT_0: 5.02
  • UOPS_PORT_1: 5.02

With blocking instructions for ports {'0', '5'}:

• Code:

     0:	0f 6f c1             	movq   mm0,mm1
     3:	0f 6f d1             	movq   mm2,mm1
     6:	0f 6f d9             	movq   mm3,mm1
     9:	0f 6f e1             	movq   mm4,mm1
     c:	0f 6f e9             	movq   mm5,mm1
     f:	0f 6f f1             	movq   mm6,mm1
    12:	0f 6f f9             	movq   mm7,mm1
    15:	0f 6f c1             	movq   mm0,mm1
    18:	0f 6f d1             	movq   mm2,mm1
    1b:	0f 6f d9             	movq   mm3,mm1
    1e:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  PXOR MM1, MM1;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2

• Show nanoBench command
• Results:
  • Instructions retired: 11.0
  • Core cycles: 5.07
  • Reference cycles: 3.84
  • UOPS_PORT_0: 5.01
  • UOPS_PORT_5B: 5.01
  • UOPS_PORT_5B>=2: 0.0

With blocking instructions for ports {'0', '6'}:

• Code:

     0:	66 41 c1 c0 00       	rol    r8w,0x0
     5:	66 41 c1 c1 00       	rol    r9w,0x0
     a:	66 41 c1 c2 00       	rol    r10w,0x0
     f:	66 41 c1 c3 00       	rol    r11w,0x0
    14:	66 41 c1 c4 00       	rol    r12w,0x0
    19:	66 c1 c3 00          	rol    bx,0x0
    1d:	66 c1 c1 00          	rol    cx,0x0
    21:	66 c1 c2 00          	rol    dx,0x0
    25:	66 41 c1 c0 00       	rol    r8w,0x0
    2a:	66 41 c1 c1 00       	rol    r9w,0x0
    2f:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2

• Show nanoBench command
• Results:
  • Instructions retired: 11.0
  • Core cycles: 5.04
  • Reference cycles: 3.84
  • UOPS_PORT_6: 4.99
  • UOPS_PORT_0: 5.01

With blocking instructions for ports {'1', '5'}:

• Code:

     0:	c5 d9 58 dd          	vaddpd xmm3,xmm4,xmm5
     4:	c5 d9 58 f5          	vaddpd xmm6,xmm4,xmm5
     8:	c5 d9 58 fd          	vaddpd xmm7,xmm4,xmm5
     c:	c5 59 58 c5          	vaddpd xmm8,xmm4,xmm5
    10:	c5 59 58 cd          	vaddpd xmm9,xmm4,xmm5
    14:	c5 59 58 d5          	vaddpd xmm10,xmm4,xmm5
    18:	c5 59 58 dd          	vaddpd xmm11,xmm4,xmm5
    1c:	c5 59 58 e5          	vaddpd xmm12,xmm4,xmm5
    20:	c5 d9 58 dd          	vaddpd xmm3,xmm4,xmm5
    24:	c5 d9 58 f5          	vaddpd xmm6,xmm4,xmm5
    28:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPD XMM4, [R14];
  VMOVUPD XMM5, [R14];
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2

• Show nanoBench command
• Results:
  • Instructions retired: 11.0
  • Core cycles: 5.06
  • Reference cycles: 3.84
  • UOPS_PORT_1: 5.02
  • UOPS_PORT_5B: 5.02
  • UOPS_PORT_5B>=2: 0.0

With blocking instructions for ports {'0', '1', '5'}:

• Code:

     0:	c5 d9 55 dd          	vandnpd xmm3,xmm4,xmm5
     4:	c5 d9 55 f5          	vandnpd xmm6,xmm4,xmm5
     8:	c5 d9 55 fd          	vandnpd xmm7,xmm4,xmm5
     c:	c5 59 55 c5          	vandnpd xmm8,xmm4,xmm5
    10:	c5 59 55 cd          	vandnpd xmm9,xmm4,xmm5
    14:	c5 59 55 d5          	vandnpd xmm10,xmm4,xmm5
    18:	c5 59 55 dd          	vandnpd xmm11,xmm4,xmm5
    1c:	c5 59 55 e5          	vandnpd xmm12,xmm4,xmm5
    20:	c5 d9 55 dd          	vandnpd xmm3,xmm4,xmm5
    24:	c5 d9 55 f5          	vandnpd xmm6,xmm4,xmm5
    28:	c5 d9 55 fd          	vandnpd xmm7,xmm4,xmm5
    2c:	c5 59 55 c5          	vandnpd xmm8,xmm4,xmm5
    30:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM4, XMM4, XMM4;
  VXORPS XMM5, XMM5, XMM5;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2

• Show nanoBench command
• Results:
  • Instructions retired: 13.0
  • Core cycles: 5.06
  • Reference cycles: 3.66
  • UOPS_PORT_1: 5.0
  • UOPS_PORT_0: 4.99
  • UOPS_PORT_5B: 5.0
  • UOPS_PORT_5B>=2: 0.0

With an indexed addressing mode

With blocking instructions for port '0':

• Code:

     0:	41 0f 7e c0          	movd   r8d,mm0
     4:	41 0f 7e c1          	movd   r9d,mm0
     8:	41 0f 7e c2          	movd   r10d,mm0
     c:	41 0f 7e c3          	movd   r11d,mm0
    10:	41 0f 7e c4          	movd   r12d,mm0
    14:	0f 7e c3             	movd   ebx,mm0
    17:	0f 7e c1             	movd   ecx,mm0
    1a:	0f 7e c2             	movd   edx,mm0
    1d:	41 0f 7e c0          	movd   r8d,mm0
    21:	41 0f 7e c1          	movd   r9d,mm0
    25:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  PXOR MM0, MM0;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 11.0
  • Core cycles: 10.02
  • Reference cycles: 7.68
  • UOPS_PORT_0: 10.0

With blocking instructions for port '1':

• Code:

     0:	44 8d 05 80 00 00 00 	lea    r8d,[rip+0x80]        # 0x87
     7:	44 8d 0d 80 00 00 00 	lea    r9d,[rip+0x80]        # 0x8e
     e:	44 8d 15 80 00 00 00 	lea    r10d,[rip+0x80]        # 0x95
    15:	44 8d 1d 80 00 00 00 	lea    r11d,[rip+0x80]        # 0x9c
    1c:	44 8d 25 80 00 00 00 	lea    r12d,[rip+0x80]        # 0xa3
    23:	8d 1d 80 00 00 00    	lea    ebx,[rip+0x80]        # 0xa9
    29:	8d 0d 80 00 00 00    	lea    ecx,[rip+0x80]        # 0xaf
    2f:	8d 15 80 00 00 00    	lea    edx,[rip+0x80]        # 0xb5
    35:	44 8d 05 80 00 00 00 	lea    r8d,[rip+0x80]        # 0xbc
    3c:	44 8d 0d 80 00 00 00 	lea    r9d,[rip+0x80]        # 0xc3
    43:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 11.0
  • Core cycles: 9.99
  • Reference cycles: 7.52
  • UOPS_PORT_1: 10.0

With blocking instructions for port '23A':

• Code:

     0:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
     4:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
     8:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
     c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
    10:	45 8b 66 50          	mov    r12d,DWORD PTR [r14+0x50]
    14:	41 8b 5e 54          	mov    ebx,DWORD PTR [r14+0x54]
    18:	41 8b 4e 58          	mov    ecx,DWORD PTR [r14+0x58]
    1c:	41 8b 56 5c          	mov    edx,DWORD PTR [r14+0x5c]
    20:	45 8b 46 40          	mov    r8d,DWORD PTR [r14+0x40]
    24:	45 8b 4e 44          	mov    r9d,DWORD PTR [r14+0x44]
    28:	45 8b 56 48          	mov    r10d,DWORD PTR [r14+0x48]
    2c:	45 8b 5e 4c          	mov    r11d,DWORD PTR [r14+0x4c]
    30:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 13.0
  • Core cycles: 4.48
  • Reference cycles: 3.47
  • UOPS_PORT_23A: 13.0

With blocking instructions for ports {'0', '1'}:

• Code:

     0:	c4 e2 59 de dd       	vaesdec xmm3,xmm4,xmm5
     5:	c4 e2 59 de f5       	vaesdec xmm6,xmm4,xmm5
     a:	c4 e2 59 de fd       	vaesdec xmm7,xmm4,xmm5
     f:	c4 62 59 de c5       	vaesdec xmm8,xmm4,xmm5
    14:	c4 62 59 de cd       	vaesdec xmm9,xmm4,xmm5
    19:	c4 62 59 de d5       	vaesdec xmm10,xmm4,xmm5
    1e:	c4 62 59 de dd       	vaesdec xmm11,xmm4,xmm5
    23:	c4 62 59 de e5       	vaesdec xmm12,xmm4,xmm5
    28:	c4 e2 59 de dd       	vaesdec xmm3,xmm4,xmm5
    2d:	c4 e2 59 de f5       	vaesdec xmm6,xmm4,xmm5
    32:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM4, XMM4, XMM4;
  VXORPS XMM5, XMM5, XMM5;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 11.0
  • Core cycles: 5.06
  • Reference cycles: 3.84
  • UOPS_PORT_0: 5.02
  • UOPS_PORT_1: 5.02

With blocking instructions for ports {'0', '5'}:

• Code:

     0:	0f 6f c1             	movq   mm0,mm1
     3:	0f 6f d1             	movq   mm2,mm1
     6:	0f 6f d9             	movq   mm3,mm1
     9:	0f 6f e1             	movq   mm4,mm1
     c:	0f 6f e9             	movq   mm5,mm1
     f:	0f 6f f1             	movq   mm6,mm1
    12:	0f 6f f9             	movq   mm7,mm1
    15:	0f 6f c1             	movq   mm0,mm1
    18:	0f 6f d1             	movq   mm2,mm1
    1b:	0f 6f d9             	movq   mm3,mm1
    1e:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  PXOR MM1, MM1;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 11.0
  • Core cycles: 5.08
  • Reference cycles: 4.0
  • UOPS_PORT_0: 5.01
  • UOPS_PORT_5B: 5.01
  • UOPS_PORT_5B>=2: 0.0

With blocking instructions for ports {'0', '6'}:

• Code:

     0:	66 41 c1 c0 00       	rol    r8w,0x0
     5:	66 41 c1 c1 00       	rol    r9w,0x0
     a:	66 41 c1 c2 00       	rol    r10w,0x0
     f:	66 41 c1 c3 00       	rol    r11w,0x0
    14:	66 41 c1 c4 00       	rol    r12w,0x0
    19:	66 c1 c3 00          	rol    bx,0x0
    1d:	66 c1 c1 00          	rol    cx,0x0
    21:	66 c1 c2 00          	rol    dx,0x0
    25:	66 41 c1 c0 00       	rol    r8w,0x0
    2a:	66 41 c1 c1 00       	rol    r9w,0x0
    2f:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 11.0
  • Core cycles: 5.03
  • Reference cycles: 3.52
  • UOPS_PORT_6: 4.99
  • UOPS_PORT_0: 5.01

With blocking instructions for ports {'1', '5'}:

• Code:

     0:	c5 d9 58 dd          	vaddpd xmm3,xmm4,xmm5
     4:	c5 d9 58 f5          	vaddpd xmm6,xmm4,xmm5
     8:	c5 d9 58 fd          	vaddpd xmm7,xmm4,xmm5
     c:	c5 59 58 c5          	vaddpd xmm8,xmm4,xmm5
    10:	c5 59 58 cd          	vaddpd xmm9,xmm4,xmm5
    14:	c5 59 58 d5          	vaddpd xmm10,xmm4,xmm5
    18:	c5 59 58 dd          	vaddpd xmm11,xmm4,xmm5
    1c:	c5 59 58 e5          	vaddpd xmm12,xmm4,xmm5
    20:	c5 d9 58 dd          	vaddpd xmm3,xmm4,xmm5
    24:	c5 d9 58 f5          	vaddpd xmm6,xmm4,xmm5
    28:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  VMOVUPD XMM4, [R14];
  VMOVUPD XMM5, [R14];
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 11.0
  • Core cycles: 5.06
  • Reference cycles: 3.84
  • UOPS_PORT_1: 5.02
  • UOPS_PORT_5B: 5.02
  • UOPS_PORT_5B>=2: 0.0

With blocking instructions for ports {'0', '1', '5'}:

• Code:

     0:	c5 d9 55 dd          	vandnpd xmm3,xmm4,xmm5
     4:	c5 d9 55 f5          	vandnpd xmm6,xmm4,xmm5
     8:	c5 d9 55 fd          	vandnpd xmm7,xmm4,xmm5
     c:	c5 59 55 c5          	vandnpd xmm8,xmm4,xmm5
    10:	c5 59 55 cd          	vandnpd xmm9,xmm4,xmm5
    14:	c5 59 55 d5          	vandnpd xmm10,xmm4,xmm5
    18:	c5 59 55 dd          	vandnpd xmm11,xmm4,xmm5
    1c:	c5 59 55 e5          	vandnpd xmm12,xmm4,xmm5
    20:	c5 d9 55 dd          	vandnpd xmm3,xmm4,xmm5
    24:	c5 d9 55 f5          	vandnpd xmm6,xmm4,xmm5
    28:	c5 d9 55 fd          	vandnpd xmm7,xmm4,xmm5
    2c:	c5 59 55 c5          	vandnpd xmm8,xmm4,xmm5
    30:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM4, XMM4, XMM4;
  VXORPS XMM5, XMM5, XMM5;
  MOV RAX, 0x4000000040000000;
  MOV [R14+0], RAX;
  MOV [R14+8], RAX;
  MOV [R14+16], RAX;
  MOV [R14+24], RAX;
  VMOVUPD YMM1, [R14];
  VXORPS YMM2, YMM2, YMM2;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 13.0
  • Core cycles: 5.06
  • Reference cycles: 3.86
  • UOPS_PORT_1: 5.0
  • UOPS_PORT_0: 5.0
  • UOPS_PORT_5B: 5.0
  • UOPS_PORT_5B>=2: 0.0