DIV (M32) - Port Usage

With blocking instructions for port '1':

Code:

   0:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
   7:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
   e:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  15:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  1c:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  23:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  2a:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  31:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  38:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  3f:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  46:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  4d:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  54:	b8 85 00 00 00       	mov    eax,0x85
  59:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
  5e:	41 f7 36             	div    DWORD PTR [r14]

Init:

VZEROALL;
MOV R8D, 0x75e6e44f;
MOV dword ptr [R14], R8D

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 16.59
- Reference cycles: 12.34
- UOPS_PORT_1: 15.01

⇨ 3 μops that can only use port '1'

With blocking instructions for port '23A':

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  81:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  88:	00 00 
  8a:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  91:	00 00 
  93:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  9a:	00 00 
  9c:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  a3:	00 00 
  a5:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  ac:	00 00 
  ae:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  b5:	00 00 
  b7:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  be:	00 00 
  c0:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  c7:	00 00 
  c9:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  d0:	00 00 
  d2:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  d8:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  de:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  e4:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  ea:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  f1:	00 00 
  f3:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  fa:	00 00 
  fc:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 103:	00 00 
 105:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 10c:	00 00 
 10e:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 115:	00 00 
 117:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 11e:	00 00 
 120:	b8 85 00 00 00       	mov    eax,0x85
 125:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
 12a:	41 f7 36             	div    DWORD PTR [r14]

Init:

VZEROALL;
MOV R8D, 0x75e6e44f;
MOV dword ptr [R14], R8D

Show nanoBench command
Results:
- Instructions retired: 39.0
- Core cycles: 13.04
- Reference cycles: 9.48
- UOPS_PORT_23A: 37.0

⇨ One μop that can only use port '23A'

With blocking instructions for ports {'0', '5'}:

Code:

   0:	0f 6f c1             	movq   mm0,mm1
   3:	0f 6f d1             	movq   mm2,mm1
   6:	0f 6f d9             	movq   mm3,mm1
   9:	0f 6f e1             	movq   mm4,mm1
   c:	0f 6f e9             	movq   mm5,mm1
   f:	0f 6f f1             	movq   mm6,mm1
  12:	0f 6f f9             	movq   mm7,mm1
  15:	0f 6f c1             	movq   mm0,mm1
  18:	0f 6f d1             	movq   mm2,mm1
  1b:	0f 6f d9             	movq   mm3,mm1
  1e:	0f 6f e1             	movq   mm4,mm1
  21:	0f 6f e9             	movq   mm5,mm1
  24:	0f 6f f1             	movq   mm6,mm1
  27:	0f 6f f9             	movq   mm7,mm1
  2a:	0f 6f c1             	movq   mm0,mm1
  2d:	0f 6f d1             	movq   mm2,mm1
  30:	0f 6f d9             	movq   mm3,mm1
  33:	0f 6f e1             	movq   mm4,mm1
  36:	0f 6f e9             	movq   mm5,mm1
  39:	0f 6f f1             	movq   mm6,mm1
  3c:	0f 6f f9             	movq   mm7,mm1
  3f:	0f 6f c1             	movq   mm0,mm1
  42:	0f 6f d1             	movq   mm2,mm1
  45:	0f 6f d9             	movq   mm3,mm1
  48:	b8 85 00 00 00       	mov    eax,0x85
  4d:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
  52:	41 f7 36             	div    DWORD PTR [r14]

Init:

PXOR MM1, MM1;
MOV R8D, 0x75e6e44f;
MOV dword ptr [R14], R8D

Show nanoBench command
Results:
- Instructions retired: 27.0
- Core cycles: 12.1
- Reference cycles: 8.59
- UOPS_PORT_0: 11.98
- UOPS_PORT_5B: 13.14
- UOPS_PORT_5B>=2: 1.11

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 41 c1 c0 00       	rol    r8w,0x0
  26:	66 41 c1 c1 00       	rol    r9w,0x0
  2b:	66 41 c1 c2 00       	rol    r10w,0x0
  30:	66 41 c1 c3 00       	rol    r11w,0x0
  35:	66 41 c1 c4 00       	rol    r12w,0x0
  3a:	66 c1 c3 00          	rol    bx,0x0
  3e:	66 c1 c1 00          	rol    cx,0x0
  42:	66 41 c1 c0 00       	rol    r8w,0x0
  47:	66 41 c1 c1 00       	rol    r9w,0x0
  4c:	66 41 c1 c2 00       	rol    r10w,0x0
  51:	66 41 c1 c3 00       	rol    r11w,0x0
  56:	66 41 c1 c4 00       	rol    r12w,0x0
  5b:	66 c1 c3 00          	rol    bx,0x0
  5f:	66 c1 c1 00          	rol    cx,0x0
  63:	66 41 c1 c0 00       	rol    r8w,0x0
  68:	66 41 c1 c1 00       	rol    r9w,0x0
  6d:	66 41 c1 c2 00       	rol    r10w,0x0
  72:	b8 85 00 00 00       	mov    eax,0x85
  77:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
  7c:	41 f7 36             	div    DWORD PTR [r14]

Init:

MOV R8D, 0x75e6e44f;
MOV dword ptr [R14], R8D

Show nanoBench command
Results:
- Instructions retired: 27.0
- Core cycles: 12.08
- Reference cycles: 8.59
- UOPS_PORT_6: 11.9
- UOPS_PORT_0: 12.02

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  30:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  35:	66 0f 55 c1          	andnpd xmm0,xmm1
  39:	66 0f 55 d1          	andnpd xmm2,xmm1
  3d:	66 0f 55 d9          	andnpd xmm3,xmm1
  41:	66 0f 55 e1          	andnpd xmm4,xmm1
  45:	66 0f 55 e9          	andnpd xmm5,xmm1
  49:	66 0f 55 f1          	andnpd xmm6,xmm1
  4d:	66 0f 55 f9          	andnpd xmm7,xmm1
  51:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  56:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  5b:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  60:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  65:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  6a:	66 0f 55 c1          	andnpd xmm0,xmm1
  6e:	66 0f 55 d1          	andnpd xmm2,xmm1
  72:	66 0f 55 d9          	andnpd xmm3,xmm1
  76:	66 0f 55 e1          	andnpd xmm4,xmm1
  7a:	66 0f 55 e9          	andnpd xmm5,xmm1
  7e:	66 0f 55 f1          	andnpd xmm6,xmm1
  82:	66 0f 55 f9          	andnpd xmm7,xmm1
  86:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  8b:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  90:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  95:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  9a:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  9f:	b8 85 00 00 00       	mov    eax,0x85
  a4:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
  a9:	41 f7 36             	div    DWORD PTR [r14]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
MOV R8D, 0x75e6e44f;
MOV dword ptr [R14], R8D

Show nanoBench command
Results:
- Instructions retired: 39.0
- Core cycles: 13.52
- Reference cycles: 9.48
- UOPS_PORT_1: 13.04
- UOPS_PORT_0: 12.96
- UOPS_PORT_5B: 14.47
- UOPS_PORT_5B>=2: 1.48

With blocking instructions for ports {'0', '5', '6'}:

Code:

   0:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
   4:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
   8:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
   c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  10:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  14:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  18:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  1c:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  20:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  24:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  28:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  2c:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  30:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  34:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  38:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  3c:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  40:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  44:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  48:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  4c:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  50:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  54:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  58:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  5c:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  60:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  64:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  68:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  6c:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  70:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  74:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  78:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  7c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  80:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  84:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  88:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  8c:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  90:	b8 85 00 00 00       	mov    eax,0x85
  95:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
  9a:	41 f7 36             	div    DWORD PTR [r14]

Init:

MOV R8D, 0x75e6e44f;
MOV dword ptr [R14], R8D

Show nanoBench command
Results:
- Instructions retired: 39.0
- Core cycles: 12.19
- Reference cycles: 8.3
- UOPS_PORT_6: 12.01
- UOPS_PORT_0: 12.0
- UOPS_PORT_5B: 13.78
- UOPS_PORT_5B>=2: 1.78

With blocking instructions for ports {'1', '5', 'B'}:

Code:

   0:	66 45 0f be c1       	movsx  r8w,r9b
   5:	66 45 0f be d1       	movsx  r10w,r9b
   a:	66 45 0f be d9       	movsx  r11w,r9b
   f:	66 45 0f be e1       	movsx  r12w,r9b
  14:	66 41 0f be d9       	movsx  bx,r9b
  19:	66 41 0f be c9       	movsx  cx,r9b
  1e:	66 45 0f be c1       	movsx  r8w,r9b
  23:	66 45 0f be d1       	movsx  r10w,r9b
  28:	66 45 0f be d9       	movsx  r11w,r9b
  2d:	66 45 0f be e1       	movsx  r12w,r9b
  32:	66 41 0f be d9       	movsx  bx,r9b
  37:	66 41 0f be c9       	movsx  cx,r9b
  3c:	66 45 0f be c1       	movsx  r8w,r9b
  41:	66 45 0f be d1       	movsx  r10w,r9b
  46:	66 45 0f be d9       	movsx  r11w,r9b
  4b:	66 45 0f be e1       	movsx  r12w,r9b
  50:	66 41 0f be d9       	movsx  bx,r9b
  55:	66 41 0f be c9       	movsx  cx,r9b
  5a:	66 45 0f be c1       	movsx  r8w,r9b
  5f:	66 45 0f be d1       	movsx  r10w,r9b
  64:	66 45 0f be d9       	movsx  r11w,r9b
  69:	66 45 0f be e1       	movsx  r12w,r9b
  6e:	66 41 0f be d9       	movsx  bx,r9b
  73:	66 41 0f be c9       	movsx  cx,r9b
  78:	66 45 0f be c1       	movsx  r8w,r9b
  7d:	66 45 0f be d1       	movsx  r10w,r9b
  82:	66 45 0f be d9       	movsx  r11w,r9b
  87:	66 45 0f be e1       	movsx  r12w,r9b
  8c:	66 41 0f be d9       	movsx  bx,r9b
  91:	66 41 0f be c9       	movsx  cx,r9b
  96:	66 45 0f be c1       	movsx  r8w,r9b
  9b:	66 45 0f be d1       	movsx  r10w,r9b
  a0:	66 45 0f be d9       	movsx  r11w,r9b
  a5:	66 45 0f be e1       	movsx  r12w,r9b
  aa:	66 41 0f be d9       	movsx  bx,r9b
  af:	66 41 0f be c9       	movsx  cx,r9b
  b4:	b8 85 00 00 00       	mov    eax,0x85
  b9:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
  be:	41 f7 36             	div    DWORD PTR [r14]

Init:

MOV R8D, 0x75e6e44f;
MOV dword ptr [R14], R8D

Show nanoBench command
Results:
- Instructions retired: 39.0
- Core cycles: 14.99
- Reference cycles: 10.67
- UOPS_PORT_1: 12.89
- UOPS_PORT_5B: 26.1

With blocking instructions for ports {'0', '1', '5', '6', 'B'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	45 8d 06             	lea    r8d,[r14]
  18:	45 8d 0e             	lea    r9d,[r14]
  1b:	45 8d 16             	lea    r10d,[r14]
  1e:	45 8d 1e             	lea    r11d,[r14]
  21:	45 8d 26             	lea    r12d,[r14]
  24:	41 8d 1e             	lea    ebx,[r14]
  27:	41 8d 0e             	lea    ecx,[r14]
  2a:	45 8d 06             	lea    r8d,[r14]
  2d:	45 8d 0e             	lea    r9d,[r14]
  30:	45 8d 16             	lea    r10d,[r14]
  33:	45 8d 1e             	lea    r11d,[r14]
  36:	45 8d 26             	lea    r12d,[r14]
  39:	41 8d 1e             	lea    ebx,[r14]
  3c:	41 8d 0e             	lea    ecx,[r14]
  3f:	45 8d 06             	lea    r8d,[r14]
  42:	45 8d 0e             	lea    r9d,[r14]
  45:	45 8d 16             	lea    r10d,[r14]
  48:	45 8d 1e             	lea    r11d,[r14]
  4b:	45 8d 26             	lea    r12d,[r14]
  4e:	41 8d 1e             	lea    ebx,[r14]
  51:	41 8d 0e             	lea    ecx,[r14]
  54:	45 8d 06             	lea    r8d,[r14]
  57:	45 8d 0e             	lea    r9d,[r14]
  5a:	45 8d 16             	lea    r10d,[r14]
  5d:	45 8d 1e             	lea    r11d,[r14]
  60:	45 8d 26             	lea    r12d,[r14]
  63:	41 8d 1e             	lea    ebx,[r14]
  66:	41 8d 0e             	lea    ecx,[r14]
  69:	45 8d 06             	lea    r8d,[r14]
  6c:	45 8d 0e             	lea    r9d,[r14]
  6f:	45 8d 16             	lea    r10d,[r14]
  72:	45 8d 1e             	lea    r11d,[r14]
  75:	45 8d 26             	lea    r12d,[r14]
  78:	41 8d 1e             	lea    ebx,[r14]
  7b:	41 8d 0e             	lea    ecx,[r14]
  7e:	45 8d 06             	lea    r8d,[r14]
  81:	45 8d 0e             	lea    r9d,[r14]
  84:	45 8d 16             	lea    r10d,[r14]
  87:	45 8d 1e             	lea    r11d,[r14]
  8a:	45 8d 26             	lea    r12d,[r14]
  8d:	41 8d 1e             	lea    ebx,[r14]
  90:	41 8d 0e             	lea    ecx,[r14]
  93:	45 8d 06             	lea    r8d,[r14]
  96:	45 8d 0e             	lea    r9d,[r14]
  99:	45 8d 16             	lea    r10d,[r14]
  9c:	45 8d 1e             	lea    r11d,[r14]
  9f:	45 8d 26             	lea    r12d,[r14]
  a2:	41 8d 1e             	lea    ebx,[r14]
  a5:	41 8d 0e             	lea    ecx,[r14]
  a8:	45 8d 06             	lea    r8d,[r14]
  ab:	45 8d 0e             	lea    r9d,[r14]
  ae:	45 8d 16             	lea    r10d,[r14]
  b1:	45 8d 1e             	lea    r11d,[r14]
  b4:	b8 85 00 00 00       	mov    eax,0x85
  b9:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
  be:	41 f7 36             	div    DWORD PTR [r14]

Init:

MOV R8D, 0x75e6e44f;
MOV dword ptr [R14], R8D

Show nanoBench command
Results:
- Instructions retired: 63.0
- Core cycles: 14.54
- Reference cycles: 12.0
- UOPS_PORT_6: 13.2
- UOPS_PORT_0: 13.33
- UOPS_PORT_1: 12.31
- UOPS_PORT_5B: 26.91

With an indexed addressing mode

With blocking instructions for port '1':

Code:

   0:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
   7:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
   e:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  15:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  1c:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  23:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  2a:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  31:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  38:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  3f:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  46:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  4d:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  54:	b8 85 00 00 00       	mov    eax,0x85
  59:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
  5e:	41 f7 36             	div    DWORD PTR [r14]

Init:

VZEROALL;
MOV R8D, 0x75e6e44f;
MOV dword ptr [R14], R8D

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 16.6
- Reference cycles: 12.53
- UOPS_PORT_1: 15.01

⇨ 3 μops that can only use port '1'

With blocking instructions for port '23A':

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  81:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  88:	00 00 
  8a:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  91:	00 00 
  93:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  9a:	00 00 
  9c:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  a3:	00 00 
  a5:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  ac:	00 00 
  ae:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  b5:	00 00 
  b7:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  be:	00 00 
  c0:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  c7:	00 00 
  c9:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  d0:	00 00 
  d2:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  d8:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  de:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  e4:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  ea:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  f1:	00 00 
  f3:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  fa:	00 00 
  fc:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
 103:	00 00 
 105:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
 10c:	00 00 
 10e:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
 115:	00 00 
 117:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
 11e:	00 00 
 120:	b8 85 00 00 00       	mov    eax,0x85
 125:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
 12a:	41 f7 36             	div    DWORD PTR [r14]

Init:

VZEROALL;
MOV R8D, 0x75e6e44f;
MOV dword ptr [R14], R8D

Show nanoBench command
Results:
- Instructions retired: 39.0
- Core cycles: 13.14
- Reference cycles: 10.67
- UOPS_PORT_23A: 37.0

⇨ One μop that can only use port '23A'

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 41 c1 c0 00       	rol    r8w,0x0
  26:	66 41 c1 c1 00       	rol    r9w,0x0
  2b:	66 41 c1 c2 00       	rol    r10w,0x0
  30:	66 41 c1 c3 00       	rol    r11w,0x0
  35:	66 41 c1 c4 00       	rol    r12w,0x0
  3a:	66 c1 c3 00          	rol    bx,0x0
  3e:	66 c1 c1 00          	rol    cx,0x0
  42:	66 41 c1 c0 00       	rol    r8w,0x0
  47:	66 41 c1 c1 00       	rol    r9w,0x0
  4c:	66 41 c1 c2 00       	rol    r10w,0x0
  51:	66 41 c1 c3 00       	rol    r11w,0x0
  56:	66 41 c1 c4 00       	rol    r12w,0x0
  5b:	66 c1 c3 00          	rol    bx,0x0
  5f:	66 c1 c1 00          	rol    cx,0x0
  63:	66 41 c1 c0 00       	rol    r8w,0x0
  68:	66 41 c1 c1 00       	rol    r9w,0x0
  6d:	66 41 c1 c2 00       	rol    r10w,0x0
  72:	b8 85 00 00 00       	mov    eax,0x85
  77:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
  7c:	41 f7 36             	div    DWORD PTR [r14]

Init:

MOV R8D, 0x75e6e44f;
MOV dword ptr [R14], R8D

Show nanoBench command
Results:
- Instructions retired: 27.0
- Core cycles: 12.08
- Reference cycles: 9.37
- UOPS_PORT_6: 11.93
- UOPS_PORT_0: 12.02

With blocking instructions for ports {'0', '5', '6'}:

Code:

   0:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
   4:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
   8:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
   c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  10:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  14:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  18:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  1c:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  20:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  24:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  28:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  2c:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  30:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  34:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  38:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  3c:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  40:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  44:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  48:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  4c:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  50:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  54:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  58:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  5c:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  60:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  64:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  68:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  6c:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  70:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  74:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  78:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  7c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  80:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  84:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  88:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  8c:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  90:	b8 85 00 00 00       	mov    eax,0x85
  95:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
  9a:	41 f7 36             	div    DWORD PTR [r14]

Init:

MOV R8D, 0x75e6e44f;
MOV dword ptr [R14], R8D

Show nanoBench command
Results:
- Instructions retired: 39.0
- Core cycles: 12.19
- Reference cycles: 10.07
- UOPS_PORT_6: 11.99
- UOPS_PORT_0: 12.0
- UOPS_PORT_5B: 13.78
- UOPS_PORT_5B>=2: 1.78

With blocking instructions for ports {'0', '1', '5', '6', 'B'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	45 8d 06             	lea    r8d,[r14]
  18:	45 8d 0e             	lea    r9d,[r14]
  1b:	45 8d 16             	lea    r10d,[r14]
  1e:	45 8d 1e             	lea    r11d,[r14]
  21:	45 8d 26             	lea    r12d,[r14]
  24:	41 8d 1e             	lea    ebx,[r14]
  27:	41 8d 0e             	lea    ecx,[r14]
  2a:	45 8d 06             	lea    r8d,[r14]
  2d:	45 8d 0e             	lea    r9d,[r14]
  30:	45 8d 16             	lea    r10d,[r14]
  33:	45 8d 1e             	lea    r11d,[r14]
  36:	45 8d 26             	lea    r12d,[r14]
  39:	41 8d 1e             	lea    ebx,[r14]
  3c:	41 8d 0e             	lea    ecx,[r14]
  3f:	45 8d 06             	lea    r8d,[r14]
  42:	45 8d 0e             	lea    r9d,[r14]
  45:	45 8d 16             	lea    r10d,[r14]
  48:	45 8d 1e             	lea    r11d,[r14]
  4b:	45 8d 26             	lea    r12d,[r14]
  4e:	41 8d 1e             	lea    ebx,[r14]
  51:	41 8d 0e             	lea    ecx,[r14]
  54:	45 8d 06             	lea    r8d,[r14]
  57:	45 8d 0e             	lea    r9d,[r14]
  5a:	45 8d 16             	lea    r10d,[r14]
  5d:	45 8d 1e             	lea    r11d,[r14]
  60:	45 8d 26             	lea    r12d,[r14]
  63:	41 8d 1e             	lea    ebx,[r14]
  66:	41 8d 0e             	lea    ecx,[r14]
  69:	45 8d 06             	lea    r8d,[r14]
  6c:	45 8d 0e             	lea    r9d,[r14]
  6f:	45 8d 16             	lea    r10d,[r14]
  72:	45 8d 1e             	lea    r11d,[r14]
  75:	45 8d 26             	lea    r12d,[r14]
  78:	41 8d 1e             	lea    ebx,[r14]
  7b:	41 8d 0e             	lea    ecx,[r14]
  7e:	45 8d 06             	lea    r8d,[r14]
  81:	45 8d 0e             	lea    r9d,[r14]
  84:	45 8d 16             	lea    r10d,[r14]
  87:	45 8d 1e             	lea    r11d,[r14]
  8a:	45 8d 26             	lea    r12d,[r14]
  8d:	41 8d 1e             	lea    ebx,[r14]
  90:	41 8d 0e             	lea    ecx,[r14]
  93:	45 8d 06             	lea    r8d,[r14]
  96:	45 8d 0e             	lea    r9d,[r14]
  99:	45 8d 16             	lea    r10d,[r14]
  9c:	45 8d 1e             	lea    r11d,[r14]
  9f:	45 8d 26             	lea    r12d,[r14]
  a2:	41 8d 1e             	lea    ebx,[r14]
  a5:	41 8d 0e             	lea    ecx,[r14]
  a8:	45 8d 06             	lea    r8d,[r14]
  ab:	45 8d 0e             	lea    r9d,[r14]
  ae:	45 8d 16             	lea    r10d,[r14]
  b1:	45 8d 1e             	lea    r11d,[r14]
  b4:	b8 85 00 00 00       	mov    eax,0x85
  b9:	ba d7 9e 3a 34       	mov    edx,0x343a9ed7
  be:	41 f7 36             	div    DWORD PTR [r14]

Init:

MOV R8D, 0x75e6e44f;
MOV dword ptr [R14], R8D

Show nanoBench command
Results:
- Instructions retired: 63.0
- Core cycles: 14.55
- Reference cycles: 10.0
- UOPS_PORT_6: 13.22
- UOPS_PORT_0: 13.35
- UOPS_PORT_1: 12.31
- UOPS_PORT_5B: 26.89