ADD (M32, I32) - Port Usage

With blocking instructions for port '23A':

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 4.42
- Reference cycles: 3.28
- UOPS_PORT_23A: 13.0

⇨ One μop that can only use port '23A'

With blocking instructions for port '49':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.73
- Reference cycles: 4.32
- UOPS_PORT_49: 11.0

⇨ One μop that can only use port '49'

With blocking instructions for port '78':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.75
- Reference cycles: 4.32
- UOPS_PORT_78: 11.0

⇨ One μop that can only use port '78'

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  30:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  35:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 4.05
- Reference cycles: 2.89
- UOPS_PORT_1: 4.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_5B: 4.65
- UOPS_PORT_5B>=2: 0.64

With blocking instructions for ports {'0', '5', '6'}:

Code:

   0:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
   4:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
   8:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
   c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  10:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  14:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  18:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  1c:	43 8d 14 6e          	lea    edx,[r14+r13*2]
  20:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  24:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  28:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  2c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  30:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 4.05
- Reference cycles: 2.7
- UOPS_PORT_6: 4.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_5B: 4.65
- UOPS_PORT_5B>=2: 0.63

With blocking instructions for ports {'0', '1', '5', '6', 'B'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	41 8d 16             	lea    edx,[r14]
  18:	45 8d 06             	lea    r8d,[r14]
  1b:	45 8d 0e             	lea    r9d,[r14]
  1e:	45 8d 16             	lea    r10d,[r14]
  21:	45 8d 1e             	lea    r11d,[r14]
  24:	45 8d 26             	lea    r12d,[r14]
  27:	41 8d 1e             	lea    ebx,[r14]
  2a:	41 8d 0e             	lea    ecx,[r14]
  2d:	41 8d 16             	lea    edx,[r14]
  30:	45 8d 06             	lea    r8d,[r14]
  33:	45 8d 0e             	lea    r9d,[r14]
  36:	45 8d 16             	lea    r10d,[r14]
  39:	45 8d 1e             	lea    r11d,[r14]
  3c:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 21.0
- Core cycles: 4.32
- Reference cycles: 2.56
- UOPS_PORT_6: 4.24
- UOPS_PORT_0: 4.18
- UOPS_PORT_1: 4.18
- UOPS_PORT_5B: 8.42

⇨ One μop that can only use ports {'0', '1', '5', '6', 'B'}

With an indexed addressing mode

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	0f 7e c2             	movd   edx,mm0
  1d:	41 0f 7e c0          	movd   r8d,mm0
  21:	41 0f 7e c1          	movd   r9d,mm0
  25:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  2c:	01

Init:
```
PXOR MM0, MM0;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.03
- Reference cycles: 7.84
- UOPS_PORT_0: 10.0

With blocking instructions for port '1':

Code:

   0:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
   7:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
   e:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  15:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  1c:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  23:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  2a:	66 f2 41 0f 38 f1 d1 	crc32  edx,r9w
  31:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  38:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  3f:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  46:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  4d:	01

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.01
- Reference cycles: 7.68
- UOPS_PORT_1: 10.01

With blocking instructions for port '23A':

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  67:	01

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 5.97
- Reference cycles: 4.43
- UOPS_PORT_23A: 13.0

⇨ One μop that can only use port '23A'

With blocking instructions for port '49':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  35:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 6.63
- Reference cycles: 4.96
- UOPS_PORT_49: 12.17

⇨ 2 μops that can only use port '49'

With blocking instructions for port '78':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  35:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 6.35
- Reference cycles: 4.48
- UOPS_PORT_78: 11.0

⇨ One μop that can only use port '78'

With blocking instructions for ports {'0', '1'}:

Code:

   0:	66 0f 38 de c1       	aesdec xmm0,xmm1
   5:	66 0f 38 de d1       	aesdec xmm2,xmm1
   a:	66 0f 38 de d9       	aesdec xmm3,xmm1
   f:	66 0f 38 de e1       	aesdec xmm4,xmm1
  14:	66 0f 38 de e9       	aesdec xmm5,xmm1
  19:	66 0f 38 de f1       	aesdec xmm6,xmm1
  1e:	66 0f 38 de f9       	aesdec xmm7,xmm1
  23:	66 44 0f 38 de c1    	aesdec xmm8,xmm1
  29:	66 44 0f 38 de c9    	aesdec xmm9,xmm1
  2f:	66 44 0f 38 de d1    	aesdec xmm10,xmm1
  35:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  3c:	01

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 6.97
- Reference cycles: 5.12
- UOPS_PORT_0: 5.02
- UOPS_PORT_1: 5.04

With blocking instructions for ports {'0', '5'}:

Code:

   0:	0f 6f c1             	movq   mm0,mm1
   3:	0f 6f d1             	movq   mm2,mm1
   6:	0f 6f d9             	movq   mm3,mm1
   9:	0f 6f e1             	movq   mm4,mm1
   c:	0f 6f e9             	movq   mm5,mm1
   f:	0f 6f f1             	movq   mm6,mm1
  12:	0f 6f f9             	movq   mm7,mm1
  15:	0f 6f c1             	movq   mm0,mm1
  18:	0f 6f d1             	movq   mm2,mm1
  1b:	0f 6f d9             	movq   mm3,mm1
  1e:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  25:	01

Init:
```
PXOR MM1, MM1;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 6.6
- Reference cycles: 4.64
- UOPS_PORT_0: 5.01
- UOPS_PORT_5B: 8.18
- UOPS_PORT_5B>=2: 2.56

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 c1 c2 00          	rol    dx,0x0
  25:	66 41 c1 c0 00       	rol    r8w,0x0
  2a:	66 41 c1 c1 00       	rol    r9w,0x0
  2f:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  36:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 6.7
- Reference cycles: 4.96
- UOPS_PORT_6: 5.08
- UOPS_PORT_0: 5.08

With blocking instructions for ports {'1', '5'}:

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  32:	01

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 7.08
- Reference cycles: 5.44
- UOPS_PORT_1: 5.0
- UOPS_PORT_5B: 8.16
- UOPS_PORT_5B>=2: 2.65

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  30:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  35:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  3c:	01

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 6.34
- Reference cycles: 4.63
- UOPS_PORT_1: 4.35
- UOPS_PORT_0: 4.28
- UOPS_PORT_5B: 7.66
- UOPS_PORT_5B>=2: 2.48

⇨ 2 μops that can only use ports {'0', '1', '5'}

With blocking instructions for ports {'0', '5', '6'}:

Code:

   0:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
   4:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
   8:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
   c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  10:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  14:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  18:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  1c:	43 8d 14 6e          	lea    edx,[r14+r13*2]
  20:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  24:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  28:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  2c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  30:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  37:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 6.32
- Reference cycles: 5.01
- UOPS_PORT_6: 4.3
- UOPS_PORT_0: 4.22
- UOPS_PORT_5B: 7.62
- UOPS_PORT_5B>=2: 2.39

⇨ One μop that can only use ports {'0', '5', '6'}

With blocking instructions for ports {'1', '5', 'B'}:

Code:

   0:	66 45 0f be c1       	movsx  r8w,r9b
   5:	66 45 0f be d1       	movsx  r10w,r9b
   a:	66 45 0f be d9       	movsx  r11w,r9b
   f:	66 45 0f be e1       	movsx  r12w,r9b
  14:	66 41 0f be d9       	movsx  bx,r9b
  19:	66 41 0f be c9       	movsx  cx,r9b
  1e:	66 41 0f be d1       	movsx  dx,r9b
  23:	66 45 0f be c1       	movsx  r8w,r9b
  28:	66 45 0f be d1       	movsx  r10w,r9b
  2d:	66 45 0f be d9       	movsx  r11w,r9b
  32:	66 45 0f be e1       	movsx  r12w,r9b
  37:	66 41 0f be d9       	movsx  bx,r9b
  3c:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  43:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 6.96
- Reference cycles: 5.78
- UOPS_PORT_1: 4.4
- UOPS_PORT_5B: 9.22

⇨ One μop that can only use ports {'1', '5', 'B'}

With blocking instructions for ports {'0', '1', '5', '6', 'B'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	41 8d 16             	lea    edx,[r14]
  18:	45 8d 06             	lea    r8d,[r14]
  1b:	45 8d 0e             	lea    r9d,[r14]
  1e:	45 8d 16             	lea    r10d,[r14]
  21:	45 8d 1e             	lea    r11d,[r14]
  24:	45 8d 26             	lea    r12d,[r14]
  27:	41 8d 1e             	lea    ebx,[r14]
  2a:	41 8d 0e             	lea    ecx,[r14]
  2d:	41 8d 16             	lea    edx,[r14]
  30:	45 8d 06             	lea    r8d,[r14]
  33:	45 8d 0e             	lea    r9d,[r14]
  36:	45 8d 16             	lea    r10d,[r14]
  39:	45 8d 1e             	lea    r11d,[r14]
  3c:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
  43:	01

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 21.0
- Core cycles: 5.17
- Reference cycles: 3.84
- UOPS_PORT_6: 4.33
- UOPS_PORT_0: 4.34
- UOPS_PORT_1: 4.36
- UOPS_PORT_5B: 8.71