VPTERNLOGD (XMM, XMM, XMM, I8)

Experiment 1

Instruction: VPTERNLOGD XMM0, XMM1, XMM2, 2

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- MPERF: 0.86
- APERF: 0.99
- UOPS: 1.0

Experiment 2

Instruction: VPTERNLOGD XMM0, XMM1, XMM2, 2
Chain instructions: VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2
   7:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
   b:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
   f:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  13:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  17:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- MPERF: 5.17
- APERF: 6.0
- UOPS: 6.0

Experiment 3

Instruction: VPTERNLOGD XMM0, XMM1, XMM2, 2
Chain instructions: VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2
   7:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   b:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   f:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  13:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  17:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- MPERF: 5.17
- APERF: 6.0
- UOPS: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPTERNLOGD XMM0, XMM1, XMM2, 2

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VPTERNLOGD XMM0, XMM1, XMM2, 2;
VPTERNLOGD XMM1, XMM0, XMM2, 2;
VPTERNLOGD XMM2, XMM0, XMM1, 2

Show nanoBench command
Results:
- MPERF: 0.94
- APERF: 1.0
- UOPS: 1.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VPTERNLOGD XMM0, XMM1, XMM2, 2
Chain instructions: VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2
   7:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
   b:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
   f:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  13:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  17:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VPTERNLOGD XMM0, XMM1, XMM2, 2;
VPTERNLOGD XMM1, XMM0, XMM2, 2;
VPTERNLOGD XMM2, XMM0, XMM1, 2

Show nanoBench command
Results:
- MPERF: 5.17
- APERF: 6.0
- UOPS: 6.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: VPTERNLOGD XMM0, XMM1, XMM2, 2
Chain instructions: VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	62 f3 75 08 25 c2 02 	vpternlogd xmm0,xmm1,xmm2,0x2
   7:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   b:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   f:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  13:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  17:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VPTERNLOGD XMM0, XMM1, XMM2, 2;
VPTERNLOGD XMM1, XMM0, XMM2, 2;
VPTERNLOGD XMM2, XMM0, XMM1, 2

Show nanoBench command
Results:
- MPERF: 5.25
- APERF: 6.0
- UOPS: 6.0

Latency operand 2 → 1: 2

Experiment 1

Instruction: VPTERNLOGD XMM1, XMM0, XMM2, 2
Chain instructions: VANDPD XMM0, XMM1, XMM1;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	62 f3 7d 08 25 ca 02 	vpternlogd xmm1,xmm0,xmm2,0x2
   7:	c5 f1 54 c1          	vandpd xmm0,xmm1,xmm1
   b:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
   f:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  13:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  17:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- MPERF: 6.19
- APERF: 7.1
- UOPS: 6.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VPTERNLOGD XMM1, XMM0, XMM2, 2
Chain instructions: VANDPD XMM0, XMM1, XMM1;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;;VXORPS XMM1, XMM1, XMM1
Chain latency: 5

Code:

   0:	62 f3 7d 08 25 ca 02 	vpternlogd xmm1,xmm0,xmm2,0x2
   7:	c5 f1 54 c1          	vandpd xmm0,xmm1,xmm1
   b:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
   f:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  13:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  17:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  1b:	c5 f0 57 c9          	vxorps xmm1,xmm1,xmm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- MPERF: 6.35
- APERF: 7.34
- UOPS: 7.0

Experiment 3

Instruction: VPTERNLOGD XMM1, XMM0, XMM2, 2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	62 f3 7d 08 25 ca 02 	vpternlogd xmm1,xmm0,xmm2,0x2
   7:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   b:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   f:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  13:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  17:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- MPERF: 6.03
- APERF: 7.1
- UOPS: 6.0

Experiment 4 (with dependency-breaking instructions)

Instruction: VPTERNLOGD XMM1, XMM0, XMM2, 2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;;VXORPS XMM1, XMM1, XMM1
Chain latency: 5

Code:

   0:	62 f3 7d 08 25 ca 02 	vpternlogd xmm1,xmm0,xmm2,0x2
   7:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   b:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   f:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  13:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  17:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1b:	c5 f0 57 c9          	vxorps xmm1,xmm1,xmm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- MPERF: 5.88
- APERF: 6.85
- UOPS: 7.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VPTERNLOGD XMM1, XMM0, XMM2, 2
Chain instructions: VANDPD XMM0, XMM1, XMM1;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	62 f3 7d 08 25 ca 02 	vpternlogd xmm1,xmm0,xmm2,0x2
   7:	c5 f1 54 c1          	vandpd xmm0,xmm1,xmm1
   b:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
   f:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  13:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  17:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM2, XMM2, XMM2;
VPTERNLOGD XMM1, XMM0, XMM2, 2;
VPTERNLOGD XMM0, XMM1, XMM2, 2;
VPTERNLOGD XMM2, XMM0, XMM1, 2

Show nanoBench command
Results:
- MPERF: 6.11
- APERF: 7.1
- UOPS: 6.0

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPTERNLOGD XMM1, XMM0, XMM2, 2
Chain instructions: VANDPD XMM0, XMM1, XMM1;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;;VXORPS XMM1, XMM1, XMM1
Chain latency: 5

Code:

   0:	62 f3 7d 08 25 ca 02 	vpternlogd xmm1,xmm0,xmm2,0x2
   7:	c5 f1 54 c1          	vandpd xmm0,xmm1,xmm1
   b:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
   f:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  13:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  17:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  1b:	c5 f0 57 c9          	vxorps xmm1,xmm1,xmm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM2, XMM2, XMM2;
VPTERNLOGD XMM1, XMM0, XMM2, 2;
VPTERNLOGD XMM0, XMM1, XMM2, 2;
VPTERNLOGD XMM2, XMM0, XMM1, 2

Show nanoBench command
Results:
- MPERF: 6.35
- APERF: 7.1
- UOPS: 7.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VPTERNLOGD XMM1, XMM0, XMM2, 2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	62 f3 7d 08 25 ca 02 	vpternlogd xmm1,xmm0,xmm2,0x2
   7:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   b:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   f:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  13:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  17:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM2, XMM2, XMM2;
VPTERNLOGD XMM1, XMM0, XMM2, 2;
VPTERNLOGD XMM0, XMM1, XMM2, 2;
VPTERNLOGD XMM2, XMM0, XMM1, 2

Show nanoBench command
Results:
- MPERF: 6.11
- APERF: 7.0
- UOPS: 6.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPTERNLOGD XMM1, XMM0, XMM2, 2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;;VXORPS XMM1, XMM1, XMM1
Chain latency: 5

Code:

   0:	62 f3 7d 08 25 ca 02 	vpternlogd xmm1,xmm0,xmm2,0x2
   7:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   b:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   f:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  13:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  17:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1b:	c5 f0 57 c9          	vxorps xmm1,xmm1,xmm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM2, XMM2, XMM2;
VPTERNLOGD XMM1, XMM0, XMM2, 2;
VPTERNLOGD XMM0, XMM1, XMM2, 2;
VPTERNLOGD XMM2, XMM0, XMM1, 2

Show nanoBench command
Results:
- MPERF: 5.8
- APERF: 6.9
- UOPS: 7.0

Latency operand 3 → 1: 2

Experiment 1

Instruction: VPTERNLOGD XMM1, XMM2, XMM0, 2
Chain instructions: VANDPD XMM0, XMM1, XMM1;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	62 f3 6d 08 25 c8 02 	vpternlogd xmm1,xmm2,xmm0,0x2
   7:	c5 f1 54 c1          	vandpd xmm0,xmm1,xmm1
   b:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
   f:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  13:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  17:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- MPERF: 6.11
- APERF: 7.0
- UOPS: 6.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VPTERNLOGD XMM1, XMM2, XMM0, 2
Chain instructions: VANDPD XMM0, XMM1, XMM1;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;;VXORPS XMM1, XMM1, XMM1
Chain latency: 5

Code:

   0:	62 f3 6d 08 25 c8 02 	vpternlogd xmm1,xmm2,xmm0,0x2
   7:	c5 f1 54 c1          	vandpd xmm0,xmm1,xmm1
   b:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
   f:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  13:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  17:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  1b:	c5 f0 57 c9          	vxorps xmm1,xmm1,xmm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- MPERF: 6.27
- APERF: 7.34
- UOPS: 7.0

Experiment 3

Instruction: VPTERNLOGD XMM1, XMM2, XMM0, 2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	62 f3 6d 08 25 c8 02 	vpternlogd xmm1,xmm2,xmm0,0x2
   7:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   b:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   f:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  13:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  17:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- MPERF: 6.11
- APERF: 7.01
- UOPS: 6.0

Experiment 4 (with dependency-breaking instructions)

Instruction: VPTERNLOGD XMM1, XMM2, XMM0, 2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;;VXORPS XMM1, XMM1, XMM1
Chain latency: 5

Code:

   0:	62 f3 6d 08 25 c8 02 	vpternlogd xmm1,xmm2,xmm0,0x2
   7:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   b:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   f:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  13:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  17:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1b:	c5 f0 57 c9          	vxorps xmm1,xmm1,xmm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- MPERF: 5.88
- APERF: 6.84
- UOPS: 7.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VPTERNLOGD XMM1, XMM2, XMM0, 2
Chain instructions: VANDPD XMM0, XMM1, XMM1;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	62 f3 6d 08 25 c8 02 	vpternlogd xmm1,xmm2,xmm0,0x2
   7:	c5 f1 54 c1          	vandpd xmm0,xmm1,xmm1
   b:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
   f:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  13:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  17:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM0, XMM0, XMM0;
VPTERNLOGD XMM1, XMM0, XMM2, 2;
VPTERNLOGD XMM2, XMM0, XMM1, 2;
VPTERNLOGD XMM0, XMM1, XMM2, 2

Show nanoBench command
Results:
- MPERF: 6.03
- APERF: 7.0
- UOPS: 6.0

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPTERNLOGD XMM1, XMM2, XMM0, 2
Chain instructions: VANDPD XMM0, XMM1, XMM1;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;VANDPD XMM0, XMM0, XMM0;;VXORPS XMM1, XMM1, XMM1
Chain latency: 5

Code:

   0:	62 f3 6d 08 25 c8 02 	vpternlogd xmm1,xmm2,xmm0,0x2
   7:	c5 f1 54 c1          	vandpd xmm0,xmm1,xmm1
   b:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
   f:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  13:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  17:	c5 f9 54 c0          	vandpd xmm0,xmm0,xmm0
  1b:	c5 f0 57 c9          	vxorps xmm1,xmm1,xmm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM0, XMM0, XMM0;
VPTERNLOGD XMM1, XMM0, XMM2, 2;
VPTERNLOGD XMM2, XMM0, XMM1, 2;
VPTERNLOGD XMM0, XMM1, XMM2, 2

Show nanoBench command
Results:
- MPERF: 6.11
- APERF: 7.1
- UOPS: 7.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VPTERNLOGD XMM1, XMM2, XMM0, 2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	62 f3 6d 08 25 c8 02 	vpternlogd xmm1,xmm2,xmm0,0x2
   7:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   b:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   f:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  13:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  17:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM0, XMM0, XMM0;
VPTERNLOGD XMM1, XMM0, XMM2, 2;
VPTERNLOGD XMM2, XMM0, XMM1, 2;
VPTERNLOGD XMM0, XMM1, XMM2, 2

Show nanoBench command
Results:
- MPERF: 6.11
- APERF: 7.12
- UOPS: 6.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPTERNLOGD XMM1, XMM2, XMM0, 2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;;VXORPS XMM1, XMM1, XMM1
Chain latency: 5

Code:

   0:	62 f3 6d 08 25 c8 02 	vpternlogd xmm1,xmm2,xmm0,0x2
   7:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   b:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   f:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  13:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  17:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1b:	c5 f0 57 c9          	vxorps xmm1,xmm1,xmm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM0, XMM0, XMM0;
VPTERNLOGD XMM1, XMM0, XMM2, 2;
VPTERNLOGD XMM2, XMM0, XMM1, 2;
VPTERNLOGD XMM0, XMM1, XMM2, 2

Show nanoBench command
Results:
- MPERF: 6.11
- APERF: 7.1
- UOPS: 7.0

VPTERNLOGD (XMM, XMM, XMM, I8) - Latency

Operands

Latency operand 1 → 1: 1

Latency operand 2 → 1: 2

Latency operand 3 → 1: 2

Latency operand 1 → 1: 1

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1: 2

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Latency operand 3 → 1: 2

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)