VGATHERDPS (ZMM, K, VSIB_ZMM) - Latency


Operands


Latency operand 1 → 1: 17

Latency operand 1 → 2: 16

Latency operand 2 → 1: 24

Latency operand 2 → 2: 9

Latency operand 3 → 1 (address, base register): ≤29

Latency operand 3 → 1 (address, index register): ≤35

Latency operand 3 → 1 (memory): ≤20


Latency operand 1 → 1: 17

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)


Latency operand 1 → 2: 16

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 1: 24

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 2: 9

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)


Latency operand 3 → 1 (address, base register): ≤29

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 3 → 1 (address, index register): ≤35

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 3 → 1 (memory): ≤20

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)