BSR (R64, M64) - Latency


Operands


Latency operand 1 → 1: 1

Latency operand 1 → 3: 1

Latency operand 2 → 1 (address, base register): 5

Latency operand 2 → 1 (address, index register): 5

Latency operand 2 → 1 (memory): ≤7

Latency operand 2 → 3 (address, base register): 5

Latency operand 2 → 3 (address, index register): 5

Latency operand 2 → 3 (memory): ≤7


Latency operand 1 → 1: 1

Experiment 1

Experiment 2


Latency operand 1 → 3: 1

Experiment 1


Latency operand 2 → 1 (address, base register): 5

Experiment 1


Latency operand 2 → 1 (address, index register): 5

Experiment 1


Latency operand 2 → 1 (memory): ≤7

Experiment 1


Latency operand 2 → 3 (address, base register): 5

Experiment 1


Latency operand 2 → 3 (address, index register): 5

Experiment 1


Latency operand 2 → 3 (memory): ≤7

Experiment 1