VBLENDVPD (YMM, YMM, M256, YMM)

Experiment 1

Instruction: VBLENDVPD YMM1, YMM0, ymmword ptr [R14], YMM2
Chain instructions: VANDPD YMM0, YMM1, YMM1;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 c3 7d 4b 0e 20    	vblendvpd ymm1,ymm0,YMMWORD PTR [r14],ymm2
   6:	c5 f5 54 c1          	vandpd ymm0,ymm1,ymm1
   a:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
   e:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  12:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  16:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- MPERF: 4.75
- APERF: 6.0
- UOPS: 6.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPD YMM1, YMM0, ymmword ptr [R14], YMM2
Chain instructions: VANDPD YMM0, YMM1, YMM1;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 c3 7d 4b 0e 20    	vblendvpd ymm1,ymm0,YMMWORD PTR [r14],ymm2
   6:	c5 f5 54 c1          	vandpd ymm0,ymm1,ymm1
   a:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
   e:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  12:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  16:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM2, YMM2, YMM2;
VBLENDVPD YMM0, YMM1, ymmword ptr [R14], YMM2;
VBLENDVPD YMM2, YMM0, ymmword ptr [R14], YMM1

Show nanoBench command
Results:
- MPERF: 5.0
- APERF: 6.0
- UOPS: 6.0

Latency operand 3 → 1 (address, base register): ≤9

Experiment 1

Instruction: VBLENDVPD YMM0, YMM1, ymmword ptr [R14], YMM2
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥5

Code:

   0:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- MPERF: 11.47
- APERF: 14.0
- UOPS: 6.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPD YMM0, YMM1, ymmword ptr [R14], YMM2
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥5

Code:

   0:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2;
VBLENDVPD YMM1, YMM0, ymmword ptr [R14], YMM2;
VBLENDVPD YMM2, YMM0, ymmword ptr [R14], YMM1

Show nanoBench command
Results:
- MPERF: 11.41
- APERF: 14.0
- UOPS: 6.0

Latency operand 3 → 1 (address, index register): ≤9

Experiment 1

Instruction: VBLENDVPD YMM0, YMM1, ymmword ptr [R14+R13], YMM2
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥5

Code:

   0:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2
   7:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   c:	4d 31 e5             	xor    r13,r12
   f:	4d 31 e5             	xor    r13,r12
  12:	4d 31 e5             	xor    r13,r12
  15:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2;
XOR R13, R13

Show nanoBench command
Results:
- MPERF: 11.47
- APERF: 14.0
- UOPS: 6.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPD YMM0, YMM1, ymmword ptr [R14+R13], YMM2
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥5

Code:

   0:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2
   7:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   c:	4d 31 e5             	xor    r13,r12
   f:	4d 31 e5             	xor    r13,r12
  12:	4d 31 e5             	xor    r13,r12
  15:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2;
XOR R13, R13;
VBLENDVPD YMM1, YMM0, ymmword ptr [R14], YMM2;
VBLENDVPD YMM2, YMM0, ymmword ptr [R14], YMM1

Show nanoBench command
Results:
- MPERF: 11.47
- APERF: 14.0
- UOPS: 6.0

Latency operand 3 → 1 (memory): ≤10

Experiment 1

Instruction: VBLENDVPD YMM0, YMM1, ymmword ptr [R14], YMM2
Chain instructions: VANDPD YMM13, YMM0, YMM0;VANDPD YMM13, YMM13, YMM13;VANDPD YMM13, YMM13, YMM13;VANDPD YMM13, YMM13, YMM13;VANDPD YMM13, YMM13, YMM13;VMOVUPD [R14], YMM13
Chain latency: ≥6

Code:

   0:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
   6:	c5 7d 54 e8          	vandpd ymm13,ymm0,ymm0
   a:	c4 41 15 54 ed       	vandpd ymm13,ymm13,ymm13
   f:	c4 41 15 54 ed       	vandpd ymm13,ymm13,ymm13
  14:	c4 41 15 54 ed       	vandpd ymm13,ymm13,ymm13
  19:	c4 41 15 54 ed       	vandpd ymm13,ymm13,ymm13
  1e:	c4 41 7d 11 2e       	vmovupd YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- MPERF: 13.14
- APERF: 16.0
- UOPS: 7.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPD YMM0, YMM1, ymmword ptr [R14], YMM2
Chain instructions: VANDPD YMM13, YMM0, YMM0;VANDPD YMM13, YMM13, YMM13;VANDPD YMM13, YMM13, YMM13;VANDPD YMM13, YMM13, YMM13;VANDPD YMM13, YMM13, YMM13;VMOVUPD [R14], YMM13
Chain latency: ≥6

Code:

   0:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
   6:	c5 7d 54 e8          	vandpd ymm13,ymm0,ymm0
   a:	c4 41 15 54 ed       	vandpd ymm13,ymm13,ymm13
   f:	c4 41 15 54 ed       	vandpd ymm13,ymm13,ymm13
  14:	c4 41 15 54 ed       	vandpd ymm13,ymm13,ymm13
  19:	c4 41 15 54 ed       	vandpd ymm13,ymm13,ymm13
  1e:	c4 41 7d 11 2e       	vmovupd YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2;
VBLENDVPD YMM1, YMM0, ymmword ptr [R14], YMM2;
VBLENDVPD YMM2, YMM0, ymmword ptr [R14], YMM1

Show nanoBench command
Results:
- MPERF: 13.01
- APERF: 16.0
- UOPS: 7.0

Latency operand 4 → 1: 1

Experiment 1

Instruction: VBLENDVPD YMM1, YMM2, ymmword ptr [R14], YMM0
Chain instructions: VANDPD YMM0, YMM1, YMM1;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 c3 6d 4b 0e 00    	vblendvpd ymm1,ymm2,YMMWORD PTR [r14],ymm0
   6:	c5 f5 54 c1          	vandpd ymm0,ymm1,ymm1
   a:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
   e:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  12:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  16:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- MPERF: 5.0
- APERF: 6.0
- UOPS: 6.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPD YMM1, YMM2, ymmword ptr [R14], YMM0
Chain instructions: VANDPD YMM0, YMM1, YMM1;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0;VANDPD YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 c3 6d 4b 0e 00    	vblendvpd ymm1,ymm2,YMMWORD PTR [r14],ymm0
   6:	c5 f5 54 c1          	vandpd ymm0,ymm1,ymm1
   a:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
   e:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  12:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0
  16:	c5 fd 54 c0          	vandpd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VXORPS YMM0, YMM0, YMM0;
VBLENDVPD YMM2, YMM0, ymmword ptr [R14], YMM1;
VBLENDVPD YMM0, YMM1, ymmword ptr [R14], YMM2

Show nanoBench command
Results:
- MPERF: 5.06
- APERF: 6.0
- UOPS: 6.0

VBLENDVPD (YMM, YMM, M256, YMM) - Latency

Operands

Latency operand 2 → 1: 1

Latency operand 3 → 1 (address, base register): ≤9

Latency operand 3 → 1 (address, index register): ≤9

Latency operand 3 → 1 (memory): ≤10

Latency operand 4 → 1: 1

Latency operand 2 → 1: 1

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (address, base register): ≤9

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (address, index register): ≤9

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (memory): ≤10

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 4 → 1: 1

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)