DIV (M64) - Latency


Operands


Latency operand 1 → 2 (address, base register): 14 ≤ lat ≤ 22

Latency operand 1 → 2 (address, index register): 14 ≤ lat ≤ 22

Latency operand 1 → 3 (address, base register): 14 ≤ lat ≤ 22

Latency operand 1 → 3 (address, index register): 14 ≤ lat ≤ 22

Latency operand 2 → 2: 10 ≤ lat ≤ 18

Latency operand 2 → 3: 10 ≤ lat ≤ 18

Latency operand 3 → 2: 11 ≤ lat ≤ 19

Latency operand 3 → 3: 11 ≤ lat ≤ 19


Latency operand 1 → 2 (address, base register): 14 ≤ lat ≤ 22

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 2 (address, index register): 14 ≤ lat ≤ 22

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, base register): 14 ≤ lat ≤ 22

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, index register): 14 ≤ lat ≤ 22

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 2: 10 ≤ lat ≤ 18

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 3: 10 ≤ lat ≤ 18

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 2: 11 ≤ lat ≤ 19

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 3: 11 ≤ lat ≤ 19

Experiment 1 (fast division)

Experiment 2 (slow division)