ADD (M32, I32) - Latency


Operands


Latency operand 1 → 1 (address, base register): ≤5

Latency operand 1 → 1 (address, index register): ≤5

Latency operand 1 → 1 (memory): 1

Latency operand 1 → 3 (address, base register): 5

Latency operand 1 → 3 (address, index register): 5

Latency operand 1 → 3 (memory): ≤1


Latency operand 1 → 1 (address, base register): ≤5

Experiment 1

Experiment 2 (with additional nop)


Latency operand 1 → 1 (address, index register): ≤5

Experiment 1

Experiment 2 (with additional nop)


Latency operand 1 → 1 (memory): 1

Experiment 1

Experiment 2


Latency operand 1 → 3 (address, base register): 5

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5

Experiment 6 (with dependency-breaking instructions)

Experiment 7

Experiment 8 (with dependency-breaking instructions)

Experiment 9

Experiment 10 (with dependency-breaking instructions)


Latency operand 1 → 3 (address, index register): 5

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5

Experiment 6 (with dependency-breaking instructions)

Experiment 7

Experiment 8 (with dependency-breaking instructions)

Experiment 9

Experiment 10 (with dependency-breaking instructions)


Latency operand 1 → 3 (memory): ≤1

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5