PBLENDVB (XMM, XMM)

Experiment 1

Instruction: PBLENDVB XMM0, XMM1

Code:

   0:	66 0f 38 10 c1       	pblendvb xmm0,xmm1,xmm0

Init:
```
PXOR XMM0, XMM0;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 2.0
- Reference cycles: 1.92
- UOPS_RETIRED.ANY: 2.0

Experiment 2

Instruction: PBLENDVB XMM0, XMM1
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	66 0f 38 10 c1       	pblendvb xmm0,xmm1,xmm0
   5:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:
```
PXOR XMM0, XMM0;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 11.0
- Reference cycles: 10.08
- UOPS_RETIRED.ANY: 7.0

Experiment 3

Instruction: PBLENDVB XMM0, XMM1
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	66 0f 38 10 c1       	pblendvb xmm0,xmm1,xmm0
   5:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0

Init:
```
PXOR XMM0, XMM0;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 7.0
- Reference cycles: 6.48
- UOPS_RETIRED.ANY: 7.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: PBLENDVB XMM0, XMM1

Code:

   0:	66 0f 38 10 c1       	pblendvb xmm0,xmm1,xmm0

Init:

PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PBLENDVB XMM0, XMM1;
PBLENDVB XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 2.0
- Reference cycles: 1.92
- UOPS_RETIRED.ANY: 2.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: PBLENDVB XMM0, XMM1
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	66 0f 38 10 c1       	pblendvb xmm0,xmm1,xmm0
   5:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PBLENDVB XMM0, XMM1;
PBLENDVB XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 11.0
- Reference cycles: 10.32
- UOPS_RETIRED.ANY: 7.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: PBLENDVB XMM0, XMM1
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	66 0f 38 10 c1       	pblendvb xmm0,xmm1,xmm0
   5:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0

Init:

PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PBLENDVB XMM0, XMM1;
PBLENDVB XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 7.0
- Reference cycles: 6.48
- UOPS_RETIRED.ANY: 7.0

Latency operand 2 → 1: 2

Experiment 1

Instruction: PBLENDVB XMM1, XMM0
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	66 0f 38 10 c8       	pblendvb xmm1,xmm0,xmm0
   5:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:
```
PXOR XMM1, XMM1;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 11.0
- Reference cycles: 10.16
- UOPS_RETIRED.ANY: 7.0

Experiment 2

Instruction: PBLENDVB XMM1, XMM0
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	66 0f 38 10 c8       	pblendvb xmm1,xmm0,xmm0
   5:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0

Init:
```
PXOR XMM1, XMM1;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 7.0
- Reference cycles: 6.4
- UOPS_RETIRED.ANY: 7.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: PBLENDVB XMM1, XMM0
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	66 0f 38 10 c8       	pblendvb xmm1,xmm0,xmm0
   5:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

PXOR XMM1, XMM1;
PXOR XMM0, XMM0;
PBLENDVB XMM1, XMM2;
PBLENDVB XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 11.0
- Reference cycles: 10.08
- UOPS_RETIRED.ANY: 7.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: PBLENDVB XMM1, XMM0
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	66 0f 38 10 c8       	pblendvb xmm1,xmm0,xmm0
   5:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0

Init:

PXOR XMM1, XMM1;
PXOR XMM0, XMM0;
PBLENDVB XMM1, XMM2;
PBLENDVB XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 7.0
- Reference cycles: 6.52
- UOPS_RETIRED.ANY: 7.0

Latency operand 3 → 1: 2

Experiment 1

Instruction: PBLENDVB XMM1, XMM2
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	66 0f 38 10 ca       	pblendvb xmm1,xmm2,xmm0
   5:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 11.0
- Reference cycles: 10.08
- UOPS_RETIRED.ANY: 7.0

Experiment 2

Instruction: PBLENDVB XMM1, XMM2
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	66 0f 38 10 ca       	pblendvb xmm1,xmm2,xmm0
   5:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0

Init:

PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 7.0
- Reference cycles: 6.44
- UOPS_RETIRED.ANY: 7.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: PBLENDVB XMM1, XMM2
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	66 0f 38 10 ca       	pblendvb xmm1,xmm2,xmm0
   5:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM0, XMM0;
PBLENDVB XMM1, XMM2;
PBLENDVB XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 11.0
- Reference cycles: 10.08
- UOPS_RETIRED.ANY: 7.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: PBLENDVB XMM1, XMM2
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	66 0f 38 10 ca       	pblendvb xmm1,xmm2,xmm0
   5:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0

Init:

PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM0, XMM0;
PBLENDVB XMM1, XMM2;
PBLENDVB XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 7.0
- Reference cycles: 6.52
- UOPS_RETIRED.ANY: 7.0

PBLENDVB (XMM, XMM) - Latency

Operands

Latency operand 1 → 1: 2

Latency operand 2 → 1: 2

Latency operand 3 → 1: 2

Latency operand 1 → 1: 2

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1: 2

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 2

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)