DIV (M64)

Experiment 1 (fast division)

Instruction: DIV qword ptr [R14]
Chain instructions: MOVSX R12, EAX; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; ; MOV RAX, R8;MOV RDX, R9
Chain latency: 21

Code:

   0:	49 f7 36             	div    QWORD PTR [r14]
   3:	4c 63 e0             	movsxd r12,eax
   6:	4d 31 e6             	xor    r14,r12
   9:	4d 31 e6             	xor    r14,r12
   c:	4d 31 e6             	xor    r14,r12
   f:	4d 31 e6             	xor    r14,r12
  12:	4d 31 e6             	xor    r14,r12
  15:	4d 31 e6             	xor    r14,r12
  18:	4d 31 e6             	xor    r14,r12
  1b:	4d 31 e6             	xor    r14,r12
  1e:	4d 31 e6             	xor    r14,r12
  21:	4d 31 e6             	xor    r14,r12
  24:	4d 31 e6             	xor    r14,r12
  27:	4d 31 e6             	xor    r14,r12
  2a:	4d 31 e6             	xor    r14,r12
  2d:	4d 31 e6             	xor    r14,r12
  30:	4d 31 e6             	xor    r14,r12
  33:	4d 31 e6             	xor    r14,r12
  36:	4d 31 e6             	xor    r14,r12
  39:	4d 31 e6             	xor    r14,r12
  3c:	4d 31 e6             	xor    r14,r12
  3f:	4d 31 e6             	xor    r14,r12
  42:	4c 89 c0             	mov    rax,r8
  45:	4c 89 ca             	mov    rdx,r9

Init:

MOV R8, 0;
MOV R9, 0;
MOV RCX, 1;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 24.0
- Core cycles: 52.14
- Reference cycles: 52.11
- RS_UOPS_DISPATCHED: 55.0

Experiment 2 (slow division)

Instruction: DIV qword ptr [R14]
Chain instructions: MOVSX R12, EAX; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; ; MOV RAX, R8;MOV RDX, R9
Chain latency: 21

Code:

   0:	49 f7 36             	div    QWORD PTR [r14]
   3:	4c 63 e0             	movsxd r12,eax
   6:	4d 31 e6             	xor    r14,r12
   9:	4d 31 e6             	xor    r14,r12
   c:	4d 31 e6             	xor    r14,r12
   f:	4d 31 e6             	xor    r14,r12
  12:	4d 31 e6             	xor    r14,r12
  15:	4d 31 e6             	xor    r14,r12
  18:	4d 31 e6             	xor    r14,r12
  1b:	4d 31 e6             	xor    r14,r12
  1e:	4d 31 e6             	xor    r14,r12
  21:	4d 31 e6             	xor    r14,r12
  24:	4d 31 e6             	xor    r14,r12
  27:	4d 31 e6             	xor    r14,r12
  2a:	4d 31 e6             	xor    r14,r12
  2d:	4d 31 e6             	xor    r14,r12
  30:	4d 31 e6             	xor    r14,r12
  33:	4d 31 e6             	xor    r14,r12
  36:	4d 31 e6             	xor    r14,r12
  39:	4d 31 e6             	xor    r14,r12
  3c:	4d 31 e6             	xor    r14,r12
  3f:	4d 31 e6             	xor    r14,r12
  42:	4c 89 c0             	mov    rax,r8
  45:	4c 89 ca             	mov    rdx,r9

Init:

MOV R8, 133;
MOV R9, 0x343a9ed744556677;
MOV RCX, 0x75e6e44fccddeeff;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 24.0
- Core cycles: 90.0
- Reference cycles: 90.0
- RS_UOPS_DISPATCHED: 69.0

Latency operand 1 → 2 (address, index register): 31 ≤ lat ≤ 69

Experiment 1 (fast division)

Instruction: DIV qword ptr [R14]
Chain instructions: MOVSX R12, EAX; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; ; MOV RAX, R8;MOV RDX, R9
Chain latency: 21

Code:

   0:	49 f7 36             	div    QWORD PTR [r14]
   3:	4c 63 e0             	movsxd r12,eax
   6:	4d 31 e6             	xor    r14,r12
   9:	4d 31 e6             	xor    r14,r12
   c:	4d 31 e6             	xor    r14,r12
   f:	4d 31 e6             	xor    r14,r12
  12:	4d 31 e6             	xor    r14,r12
  15:	4d 31 e6             	xor    r14,r12
  18:	4d 31 e6             	xor    r14,r12
  1b:	4d 31 e6             	xor    r14,r12
  1e:	4d 31 e6             	xor    r14,r12
  21:	4d 31 e6             	xor    r14,r12
  24:	4d 31 e6             	xor    r14,r12
  27:	4d 31 e6             	xor    r14,r12
  2a:	4d 31 e6             	xor    r14,r12
  2d:	4d 31 e6             	xor    r14,r12
  30:	4d 31 e6             	xor    r14,r12
  33:	4d 31 e6             	xor    r14,r12
  36:	4d 31 e6             	xor    r14,r12
  39:	4d 31 e6             	xor    r14,r12
  3c:	4d 31 e6             	xor    r14,r12
  3f:	4d 31 e6             	xor    r14,r12
  42:	4c 89 c0             	mov    rax,r8
  45:	4c 89 ca             	mov    rdx,r9

Init:

MOV R8, 0;
MOV R9, 0;
MOV RCX, 1;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 24.0
- Core cycles: 52.14
- Reference cycles: 52.11
- RS_UOPS_DISPATCHED: 55.0

Experiment 2 (slow division)

Instruction: DIV qword ptr [R14]
Chain instructions: MOVSX R12, EAX; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; ; MOV RAX, R8;MOV RDX, R9
Chain latency: 21

Code:

   0:	49 f7 36             	div    QWORD PTR [r14]
   3:	4c 63 e0             	movsxd r12,eax
   6:	4d 31 e6             	xor    r14,r12
   9:	4d 31 e6             	xor    r14,r12
   c:	4d 31 e6             	xor    r14,r12
   f:	4d 31 e6             	xor    r14,r12
  12:	4d 31 e6             	xor    r14,r12
  15:	4d 31 e6             	xor    r14,r12
  18:	4d 31 e6             	xor    r14,r12
  1b:	4d 31 e6             	xor    r14,r12
  1e:	4d 31 e6             	xor    r14,r12
  21:	4d 31 e6             	xor    r14,r12
  24:	4d 31 e6             	xor    r14,r12
  27:	4d 31 e6             	xor    r14,r12
  2a:	4d 31 e6             	xor    r14,r12
  2d:	4d 31 e6             	xor    r14,r12
  30:	4d 31 e6             	xor    r14,r12
  33:	4d 31 e6             	xor    r14,r12
  36:	4d 31 e6             	xor    r14,r12
  39:	4d 31 e6             	xor    r14,r12
  3c:	4d 31 e6             	xor    r14,r12
  3f:	4d 31 e6             	xor    r14,r12
  42:	4c 89 c0             	mov    rax,r8
  45:	4c 89 ca             	mov    rdx,r9

Init:

MOV R8, 133;
MOV R9, 0x343a9ed744556677;
MOV RCX, 0x75e6e44fccddeeff;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 24.0
- Core cycles: 90.0
- Reference cycles: 89.99
- RS_UOPS_DISPATCHED: 69.0

Latency operand 1 → 3 (address, base register): 30 ≤ lat ≤ 68

Experiment 1 (fast division)

Instruction: DIV qword ptr [R14]
Chain instructions: MOVSX R12, EDX; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; ; MOV RAX, R8;MOV RDX, R9
Chain latency: 21

Code:

   0:	49 f7 36             	div    QWORD PTR [r14]
   3:	4c 63 e2             	movsxd r12,edx
   6:	4d 31 e6             	xor    r14,r12
   9:	4d 31 e6             	xor    r14,r12
   c:	4d 31 e6             	xor    r14,r12
   f:	4d 31 e6             	xor    r14,r12
  12:	4d 31 e6             	xor    r14,r12
  15:	4d 31 e6             	xor    r14,r12
  18:	4d 31 e6             	xor    r14,r12
  1b:	4d 31 e6             	xor    r14,r12
  1e:	4d 31 e6             	xor    r14,r12
  21:	4d 31 e6             	xor    r14,r12
  24:	4d 31 e6             	xor    r14,r12
  27:	4d 31 e6             	xor    r14,r12
  2a:	4d 31 e6             	xor    r14,r12
  2d:	4d 31 e6             	xor    r14,r12
  30:	4d 31 e6             	xor    r14,r12
  33:	4d 31 e6             	xor    r14,r12
  36:	4d 31 e6             	xor    r14,r12
  39:	4d 31 e6             	xor    r14,r12
  3c:	4d 31 e6             	xor    r14,r12
  3f:	4d 31 e6             	xor    r14,r12
  42:	4c 89 c0             	mov    rax,r8
  45:	4c 89 ca             	mov    rdx,r9

Init:

MOV R8, 0;
MOV R9, 0;
MOV RCX, 1;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 24.0
- Core cycles: 51.26
- Reference cycles: 51.24
- RS_UOPS_DISPATCHED: 55.0

Experiment 2 (slow division)

Instruction: DIV qword ptr [R14]
Chain instructions: MOVSX R12, EDX; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; ; MOV RAX, R8;MOV RDX, R9
Chain latency: 21

Code:

   0:	49 f7 36             	div    QWORD PTR [r14]
   3:	4c 63 e2             	movsxd r12,edx
   6:	4d 31 e6             	xor    r14,r12
   9:	4d 31 e6             	xor    r14,r12
   c:	4d 31 e6             	xor    r14,r12
   f:	4d 31 e6             	xor    r14,r12
  12:	4d 31 e6             	xor    r14,r12
  15:	4d 31 e6             	xor    r14,r12
  18:	4d 31 e6             	xor    r14,r12
  1b:	4d 31 e6             	xor    r14,r12
  1e:	4d 31 e6             	xor    r14,r12
  21:	4d 31 e6             	xor    r14,r12
  24:	4d 31 e6             	xor    r14,r12
  27:	4d 31 e6             	xor    r14,r12
  2a:	4d 31 e6             	xor    r14,r12
  2d:	4d 31 e6             	xor    r14,r12
  30:	4d 31 e6             	xor    r14,r12
  33:	4d 31 e6             	xor    r14,r12
  36:	4d 31 e6             	xor    r14,r12
  39:	4d 31 e6             	xor    r14,r12
  3c:	4d 31 e6             	xor    r14,r12
  3f:	4d 31 e6             	xor    r14,r12
  42:	4c 89 c0             	mov    rax,r8
  45:	4c 89 ca             	mov    rdx,r9

Init:

MOV R8, 133;
MOV R9, 0x343a9ed744556677;
MOV RCX, 0x75e6e44fccddeeff;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 24.0
- Core cycles: 89.5
- Reference cycles: 89.54
- RS_UOPS_DISPATCHED: 69.0

Latency operand 1 → 3 (address, index register): 30 ≤ lat ≤ 68

Experiment 1 (fast division)

Instruction: DIV qword ptr [R14]
Chain instructions: MOVSX R12, EDX; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; ; MOV RAX, R8;MOV RDX, R9
Chain latency: 21

Code:

   0:	49 f7 36             	div    QWORD PTR [r14]
   3:	4c 63 e2             	movsxd r12,edx
   6:	4d 31 e6             	xor    r14,r12
   9:	4d 31 e6             	xor    r14,r12
   c:	4d 31 e6             	xor    r14,r12
   f:	4d 31 e6             	xor    r14,r12
  12:	4d 31 e6             	xor    r14,r12
  15:	4d 31 e6             	xor    r14,r12
  18:	4d 31 e6             	xor    r14,r12
  1b:	4d 31 e6             	xor    r14,r12
  1e:	4d 31 e6             	xor    r14,r12
  21:	4d 31 e6             	xor    r14,r12
  24:	4d 31 e6             	xor    r14,r12
  27:	4d 31 e6             	xor    r14,r12
  2a:	4d 31 e6             	xor    r14,r12
  2d:	4d 31 e6             	xor    r14,r12
  30:	4d 31 e6             	xor    r14,r12
  33:	4d 31 e6             	xor    r14,r12
  36:	4d 31 e6             	xor    r14,r12
  39:	4d 31 e6             	xor    r14,r12
  3c:	4d 31 e6             	xor    r14,r12
  3f:	4d 31 e6             	xor    r14,r12
  42:	4c 89 c0             	mov    rax,r8
  45:	4c 89 ca             	mov    rdx,r9

Init:

MOV R8, 0;
MOV R9, 0;
MOV RCX, 1;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 24.0
- Core cycles: 51.26
- Reference cycles: 51.24
- RS_UOPS_DISPATCHED: 55.0

Experiment 2 (slow division)

Instruction: DIV qword ptr [R14]
Chain instructions: MOVSX R12, EDX; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; XOR R14, R12; ; MOV RAX, R8;MOV RDX, R9
Chain latency: 21

Code:

   0:	49 f7 36             	div    QWORD PTR [r14]
   3:	4c 63 e2             	movsxd r12,edx
   6:	4d 31 e6             	xor    r14,r12
   9:	4d 31 e6             	xor    r14,r12
   c:	4d 31 e6             	xor    r14,r12
   f:	4d 31 e6             	xor    r14,r12
  12:	4d 31 e6             	xor    r14,r12
  15:	4d 31 e6             	xor    r14,r12
  18:	4d 31 e6             	xor    r14,r12
  1b:	4d 31 e6             	xor    r14,r12
  1e:	4d 31 e6             	xor    r14,r12
  21:	4d 31 e6             	xor    r14,r12
  24:	4d 31 e6             	xor    r14,r12
  27:	4d 31 e6             	xor    r14,r12
  2a:	4d 31 e6             	xor    r14,r12
  2d:	4d 31 e6             	xor    r14,r12
  30:	4d 31 e6             	xor    r14,r12
  33:	4d 31 e6             	xor    r14,r12
  36:	4d 31 e6             	xor    r14,r12
  39:	4d 31 e6             	xor    r14,r12
  3c:	4d 31 e6             	xor    r14,r12
  3f:	4d 31 e6             	xor    r14,r12
  42:	4c 89 c0             	mov    rax,r8
  45:	4c 89 ca             	mov    rdx,r9

Init:

MOV R8, 133;
MOV R9, 0x343a9ed744556677;
MOV RCX, 0x75e6e44fccddeeff;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 24.0
- Core cycles: 89.5
- Reference cycles: 89.54
- RS_UOPS_DISPATCHED: 69.0

Latency operand 2 → 2: 27 ≤ lat ≤ 66

Experiment 1 (fast division)

Instruction: DIV qword ptr [R14]
Chain instructions: AND RAX, R8; OR RAX, R8; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; ; MOV RDX, R9
Chain latency: 22

Code:

   0:	49 f7 36             	div    QWORD PTR [r14]
   3:	4c 21 c0             	and    rax,r8
   6:	4c 09 c0             	or     rax,r8
   9:	48 09 c0             	or     rax,rax
   c:	48 09 c0             	or     rax,rax
   f:	48 09 c0             	or     rax,rax
  12:	48 09 c0             	or     rax,rax
  15:	48 09 c0             	or     rax,rax
  18:	48 09 c0             	or     rax,rax
  1b:	48 09 c0             	or     rax,rax
  1e:	48 09 c0             	or     rax,rax
  21:	48 09 c0             	or     rax,rax
  24:	48 09 c0             	or     rax,rax
  27:	48 09 c0             	or     rax,rax
  2a:	48 09 c0             	or     rax,rax
  2d:	48 09 c0             	or     rax,rax
  30:	48 09 c0             	or     rax,rax
  33:	48 09 c0             	or     rax,rax
  36:	48 09 c0             	or     rax,rax
  39:	48 09 c0             	or     rax,rax
  3c:	48 09 c0             	or     rax,rax
  3f:	48 09 c0             	or     rax,rax
  42:	48 09 c0             	or     rax,rax
  45:	4c 89 ca             	mov    rdx,r9

Init:

MOV R8, 0;
MOV R9, 0;
MOV RCX, 1;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 24.0
- Core cycles: 49.0
- Reference cycles: 48.96
- RS_UOPS_DISPATCHED: 55.0

Experiment 2 (slow division)

Instruction: DIV qword ptr [R14]
Chain instructions: AND RAX, R8; OR RAX, R8; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; ; MOV RDX, R9
Chain latency: 22

Code:

   0:	49 f7 36             	div    QWORD PTR [r14]
   3:	4c 21 c0             	and    rax,r8
   6:	4c 09 c0             	or     rax,r8
   9:	48 09 c0             	or     rax,rax
   c:	48 09 c0             	or     rax,rax
   f:	48 09 c0             	or     rax,rax
  12:	48 09 c0             	or     rax,rax
  15:	48 09 c0             	or     rax,rax
  18:	48 09 c0             	or     rax,rax
  1b:	48 09 c0             	or     rax,rax
  1e:	48 09 c0             	or     rax,rax
  21:	48 09 c0             	or     rax,rax
  24:	48 09 c0             	or     rax,rax
  27:	48 09 c0             	or     rax,rax
  2a:	48 09 c0             	or     rax,rax
  2d:	48 09 c0             	or     rax,rax
  30:	48 09 c0             	or     rax,rax
  33:	48 09 c0             	or     rax,rax
  36:	48 09 c0             	or     rax,rax
  39:	48 09 c0             	or     rax,rax
  3c:	48 09 c0             	or     rax,rax
  3f:	48 09 c0             	or     rax,rax
  42:	48 09 c0             	or     rax,rax
  45:	4c 89 ca             	mov    rdx,r9

Init:

MOV R8, 133;
MOV R9, 0x343a9ed744556677;
MOV RCX, 0x75e6e44fccddeeff;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 24.0
- Core cycles: 88.0
- Reference cycles: 88.01
- RS_UOPS_DISPATCHED: 70.0

Latency operand 2 → 3: 28 ≤ lat ≤ 66

Experiment 1 (fast division)

Instruction: DIV qword ptr [R14]
Chain instructions: AND RAX, RDX; AND RAX, R8; OR RAX, R8; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; ; MOV RDX, R9
Chain latency: 23

Code:

   0:	49 f7 36             	div    QWORD PTR [r14]
   3:	48 21 d0             	and    rax,rdx
   6:	4c 21 c0             	and    rax,r8
   9:	4c 09 c0             	or     rax,r8
   c:	48 09 c0             	or     rax,rax
   f:	48 09 c0             	or     rax,rax
  12:	48 09 c0             	or     rax,rax
  15:	48 09 c0             	or     rax,rax
  18:	48 09 c0             	or     rax,rax
  1b:	48 09 c0             	or     rax,rax
  1e:	48 09 c0             	or     rax,rax
  21:	48 09 c0             	or     rax,rax
  24:	48 09 c0             	or     rax,rax
  27:	48 09 c0             	or     rax,rax
  2a:	48 09 c0             	or     rax,rax
  2d:	48 09 c0             	or     rax,rax
  30:	48 09 c0             	or     rax,rax
  33:	48 09 c0             	or     rax,rax
  36:	48 09 c0             	or     rax,rax
  39:	48 09 c0             	or     rax,rax
  3c:	48 09 c0             	or     rax,rax
  3f:	48 09 c0             	or     rax,rax
  42:	48 09 c0             	or     rax,rax
  45:	48 09 c0             	or     rax,rax
  48:	4c 89 ca             	mov    rdx,r9

Init:

MOV R8, 0;
MOV R9, 0;
MOV RCX, 1;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 51.16
- Reference cycles: 51.15
- RS_UOPS_DISPATCHED: 56.0

Experiment 2 (slow division)

Instruction: DIV qword ptr [R14]
Chain instructions: AND RAX, RDX; AND RAX, R8; OR RAX, R8; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; OR RAX, RAX; ; MOV RDX, R9
Chain latency: 23

Code:

   0:	49 f7 36             	div    QWORD PTR [r14]
   3:	48 21 d0             	and    rax,rdx
   6:	4c 21 c0             	and    rax,r8
   9:	4c 09 c0             	or     rax,r8
   c:	48 09 c0             	or     rax,rax
   f:	48 09 c0             	or     rax,rax
  12:	48 09 c0             	or     rax,rax
  15:	48 09 c0             	or     rax,rax
  18:	48 09 c0             	or     rax,rax
  1b:	48 09 c0             	or     rax,rax
  1e:	48 09 c0             	or     rax,rax
  21:	48 09 c0             	or     rax,rax
  24:	48 09 c0             	or     rax,rax
  27:	48 09 c0             	or     rax,rax
  2a:	48 09 c0             	or     rax,rax
  2d:	48 09 c0             	or     rax,rax
  30:	48 09 c0             	or     rax,rax
  33:	48 09 c0             	or     rax,rax
  36:	48 09 c0             	or     rax,rax
  39:	48 09 c0             	or     rax,rax
  3c:	48 09 c0             	or     rax,rax
  3f:	48 09 c0             	or     rax,rax
  42:	48 09 c0             	or     rax,rax
  45:	48 09 c0             	or     rax,rax
  48:	4c 89 ca             	mov    rdx,r9

Init:

MOV R8, 133;
MOV R9, 0x343a9ed744556677;
MOV RCX, 0x75e6e44fccddeeff;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 89.0
- Reference cycles: 89.0
- RS_UOPS_DISPATCHED: 70.5

Latency operand 3 → 2: 12 ≤ lat ≤ 61

Experiment 1 (fast division)

Instruction: DIV qword ptr [R14]
Chain instructions: AND RDX, RAX; AND RDX, R9; OR RDX, R9; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; ; MOV RAX, R8
Chain latency: 23

Code:

   0:	49 f7 36             	div    QWORD PTR [r14]
   3:	48 21 c2             	and    rdx,rax
   6:	4c 21 ca             	and    rdx,r9
   9:	4c 09 ca             	or     rdx,r9
   c:	48 09 d2             	or     rdx,rdx
   f:	48 09 d2             	or     rdx,rdx
  12:	48 09 d2             	or     rdx,rdx
  15:	48 09 d2             	or     rdx,rdx
  18:	48 09 d2             	or     rdx,rdx
  1b:	48 09 d2             	or     rdx,rdx
  1e:	48 09 d2             	or     rdx,rdx
  21:	48 09 d2             	or     rdx,rdx
  24:	48 09 d2             	or     rdx,rdx
  27:	48 09 d2             	or     rdx,rdx
  2a:	48 09 d2             	or     rdx,rdx
  2d:	48 09 d2             	or     rdx,rdx
  30:	48 09 d2             	or     rdx,rdx
  33:	48 09 d2             	or     rdx,rdx
  36:	48 09 d2             	or     rdx,rdx
  39:	48 09 d2             	or     rdx,rdx
  3c:	48 09 d2             	or     rdx,rdx
  3f:	48 09 d2             	or     rdx,rdx
  42:	48 09 d2             	or     rdx,rdx
  45:	48 09 d2             	or     rdx,rdx
  48:	4c 89 c0             	mov    rax,r8

Init:

MOV R8, 0;
MOV R9, 0;
MOV RCX, 1;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 34.92
- Reference cycles: 34.92
- RS_UOPS_DISPATCHED: 56.0

Experiment 2 (slow division)

Instruction: DIV qword ptr [R14]
Chain instructions: AND RDX, RAX; AND RDX, R9; OR RDX, R9; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; ; MOV RAX, R8
Chain latency: 23

Code:

   0:	49 f7 36             	div    QWORD PTR [r14]
   3:	48 21 c2             	and    rdx,rax
   6:	4c 21 ca             	and    rdx,r9
   9:	4c 09 ca             	or     rdx,r9
   c:	48 09 d2             	or     rdx,rdx
   f:	48 09 d2             	or     rdx,rdx
  12:	48 09 d2             	or     rdx,rdx
  15:	48 09 d2             	or     rdx,rdx
  18:	48 09 d2             	or     rdx,rdx
  1b:	48 09 d2             	or     rdx,rdx
  1e:	48 09 d2             	or     rdx,rdx
  21:	48 09 d2             	or     rdx,rdx
  24:	48 09 d2             	or     rdx,rdx
  27:	48 09 d2             	or     rdx,rdx
  2a:	48 09 d2             	or     rdx,rdx
  2d:	48 09 d2             	or     rdx,rdx
  30:	48 09 d2             	or     rdx,rdx
  33:	48 09 d2             	or     rdx,rdx
  36:	48 09 d2             	or     rdx,rdx
  39:	48 09 d2             	or     rdx,rdx
  3c:	48 09 d2             	or     rdx,rdx
  3f:	48 09 d2             	or     rdx,rdx
  42:	48 09 d2             	or     rdx,rdx
  45:	48 09 d2             	or     rdx,rdx
  48:	4c 89 c0             	mov    rax,r8

Init:

MOV R8, 133;
MOV R9, 0x343a9ed744556677;
MOV RCX, 0x75e6e44fccddeeff;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 84.0
- Reference cycles: 84.0
- RS_UOPS_DISPATCHED: 74.0

Latency operand 3 → 3: 11 ≤ lat ≤ 68

Experiment 1 (fast division)

Instruction: DIV qword ptr [R14]
Chain instructions: AND RDX, R9; OR RDX, R9; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; ; MOV RAX, R8
Chain latency: 22

Code:

   0:	49 f7 36             	div    QWORD PTR [r14]
   3:	4c 21 ca             	and    rdx,r9
   6:	4c 09 ca             	or     rdx,r9
   9:	48 09 d2             	or     rdx,rdx
   c:	48 09 d2             	or     rdx,rdx
   f:	48 09 d2             	or     rdx,rdx
  12:	48 09 d2             	or     rdx,rdx
  15:	48 09 d2             	or     rdx,rdx
  18:	48 09 d2             	or     rdx,rdx
  1b:	48 09 d2             	or     rdx,rdx
  1e:	48 09 d2             	or     rdx,rdx
  21:	48 09 d2             	or     rdx,rdx
  24:	48 09 d2             	or     rdx,rdx
  27:	48 09 d2             	or     rdx,rdx
  2a:	48 09 d2             	or     rdx,rdx
  2d:	48 09 d2             	or     rdx,rdx
  30:	48 09 d2             	or     rdx,rdx
  33:	48 09 d2             	or     rdx,rdx
  36:	48 09 d2             	or     rdx,rdx
  39:	48 09 d2             	or     rdx,rdx
  3c:	48 09 d2             	or     rdx,rdx
  3f:	48 09 d2             	or     rdx,rdx
  42:	48 09 d2             	or     rdx,rdx
  45:	4c 89 c0             	mov    rax,r8

Init:

MOV R8, 0;
MOV R9, 0;
MOV RCX, 1;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 24.0
- Core cycles: 32.87
- Reference cycles: 32.87
- RS_UOPS_DISPATCHED: 55.0

Experiment 2 (slow division)

Instruction: DIV qword ptr [R14]
Chain instructions: AND RDX, R9; OR RDX, R9; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; OR RDX, RDX; ; MOV RAX, R8
Chain latency: 22

Code:

   0:	49 f7 36             	div    QWORD PTR [r14]
   3:	4c 21 ca             	and    rdx,r9
   6:	4c 09 ca             	or     rdx,r9
   9:	48 09 d2             	or     rdx,rdx
   c:	48 09 d2             	or     rdx,rdx
   f:	48 09 d2             	or     rdx,rdx
  12:	48 09 d2             	or     rdx,rdx
  15:	48 09 d2             	or     rdx,rdx
  18:	48 09 d2             	or     rdx,rdx
  1b:	48 09 d2             	or     rdx,rdx
  1e:	48 09 d2             	or     rdx,rdx
  21:	48 09 d2             	or     rdx,rdx
  24:	48 09 d2             	or     rdx,rdx
  27:	48 09 d2             	or     rdx,rdx
  2a:	48 09 d2             	or     rdx,rdx
  2d:	48 09 d2             	or     rdx,rdx
  30:	48 09 d2             	or     rdx,rdx
  33:	48 09 d2             	or     rdx,rdx
  36:	48 09 d2             	or     rdx,rdx
  39:	48 09 d2             	or     rdx,rdx
  3c:	48 09 d2             	or     rdx,rdx
  3f:	48 09 d2             	or     rdx,rdx
  42:	48 09 d2             	or     rdx,rdx
  45:	4c 89 c0             	mov    rax,r8

Init:

MOV R8, 133;
MOV R9, 0x343a9ed744556677;
MOV RCX, 0x75e6e44fccddeeff;
MOV [R14], RCX;
MOV RAX, R8;
MOV RDX, R9

Show nanoBench command
Results:
- Instructions retired: 24.0
- Core cycles: 90.0
- Reference cycles: 90.0
- RS_UOPS_DISPATCHED: 95.0

DIV (M64) - Latency

Operands

Latency operand 1 → 2 (address, base register): 31 ≤ lat ≤ 69

Latency operand 1 → 2 (address, index register): 31 ≤ lat ≤ 69

Latency operand 1 → 3 (address, base register): 30 ≤ lat ≤ 68

Latency operand 1 → 3 (address, index register): 30 ≤ lat ≤ 68

Latency operand 2 → 2: 27 ≤ lat ≤ 66

Latency operand 2 → 3: 28 ≤ lat ≤ 66

Latency operand 3 → 2: 12 ≤ lat ≤ 61

Latency operand 3 → 3: 11 ≤ lat ≤ 68

Latency operand 1 → 2 (address, base register): 31 ≤ lat ≤ 69

Experiment 1 (fast division)

Experiment 2 (slow division)

Latency operand 1 → 2 (address, index register): 31 ≤ lat ≤ 69

Experiment 1 (fast division)

Experiment 2 (slow division)

Latency operand 1 → 3 (address, base register): 30 ≤ lat ≤ 68

Experiment 1 (fast division)

Experiment 2 (slow division)

Latency operand 1 → 3 (address, index register): 30 ≤ lat ≤ 68

Experiment 1 (fast division)

Experiment 2 (slow division)

Latency operand 2 → 2: 27 ≤ lat ≤ 66

Experiment 1 (fast division)

Experiment 2 (slow division)

Latency operand 2 → 3: 28 ≤ lat ≤ 66

Experiment 1 (fast division)

Experiment 2 (slow division)

Latency operand 3 → 2: 12 ≤ lat ≤ 61

Experiment 1 (fast division)

Experiment 2 (slow division)

Latency operand 3 → 3: 11 ≤ lat ≤ 68

Experiment 1 (fast division)

Experiment 2 (slow division)