PCLMULQDQ (XMM, XMM, I8)

Experiment 1

Instruction: PCLMULQDQ XMM0, XMM1, 2

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1

Init:
```
PXOR XMM0, XMM0;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.99
- Reference cycles: 2.34
- TOPDOWN_RETIRING.ALL: 1.0

Experiment 2

Instruction: PCLMULQDQ XMM0, XMM1, 2
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 7

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   b:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  10:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  15:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  24:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:
```
PXOR XMM0, XMM0;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.99
- Reference cycles: 6.5
- TOPDOWN_RETIRING.ALL: 8.0

Experiment 3

Instruction: PCLMULQDQ XMM0, XMM1, 2
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 7

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   b:	66 0f db c0          	pand   xmm0,xmm0
   f:	66 0f db c0          	pand   xmm0,xmm0
  13:	66 0f db c0          	pand   xmm0,xmm0
  17:	66 0f db c0          	pand   xmm0,xmm0
  1b:	66 0f db c0          	pand   xmm0,xmm0
  1f:	66 0f db c0          	pand   xmm0,xmm0

Init:
```
PXOR XMM0, XMM0;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 6.5
- TOPDOWN_RETIRING.ALL: 8.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: PCLMULQDQ XMM0, XMM1, 2

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1

Init:

PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PCLMULQDQ XMM0, XMM1, 2;
PCLMULQDQ XMM1, XMM0, 2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 2.43
- TOPDOWN_RETIRING.ALL: 1.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: PCLMULQDQ XMM0, XMM1, 2
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 7

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   b:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  10:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  15:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  24:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PCLMULQDQ XMM0, XMM1, 2;
PCLMULQDQ XMM1, XMM0, 2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 6.67
- TOPDOWN_RETIRING.ALL: 8.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: PCLMULQDQ XMM0, XMM1, 2
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 7

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   b:	66 0f db c0          	pand   xmm0,xmm0
   f:	66 0f db c0          	pand   xmm0,xmm0
  13:	66 0f db c0          	pand   xmm0,xmm0
  17:	66 0f db c0          	pand   xmm0,xmm0
  1b:	66 0f db c0          	pand   xmm0,xmm0
  1f:	66 0f db c0          	pand   xmm0,xmm0

Init:

PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PCLMULQDQ XMM0, XMM1, 2;
PCLMULQDQ XMM1, XMM0, 2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 6.76
- TOPDOWN_RETIRING.ALL: 8.0

Experiment 1

Instruction: PCLMULQDQ XMM1, XMM0, 2
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 7

Code:

   0:	66 0f 3a 44 c8 02    	pclmullqhqdq xmm1,xmm0
   6:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   b:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  10:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  15:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  24:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:
```
PXOR XMM1, XMM1;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 6.59
- TOPDOWN_RETIRING.ALL: 8.0

Experiment 2

Instruction: PCLMULQDQ XMM1, XMM0, 2
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 7

Code:

   0:	66 0f 3a 44 c8 02    	pclmullqhqdq xmm1,xmm0
   6:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   b:	66 0f db c0          	pand   xmm0,xmm0
   f:	66 0f db c0          	pand   xmm0,xmm0
  13:	66 0f db c0          	pand   xmm0,xmm0
  17:	66 0f db c0          	pand   xmm0,xmm0
  1b:	66 0f db c0          	pand   xmm0,xmm0
  1f:	66 0f db c0          	pand   xmm0,xmm0

Init:
```
PXOR XMM1, XMM1;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 6.5
- TOPDOWN_RETIRING.ALL: 8.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: PCLMULQDQ XMM1, XMM0, 2
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 7

Code:

   0:	66 0f 3a 44 c8 02    	pclmullqhqdq xmm1,xmm0
   6:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   b:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  10:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  15:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  24:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

PXOR XMM1, XMM1;
PXOR XMM0, XMM0;
PCLMULQDQ XMM1, XMM0, 2;
PCLMULQDQ XMM0, XMM1, 2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 6.5
- TOPDOWN_RETIRING.ALL: 8.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: PCLMULQDQ XMM1, XMM0, 2
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 7

Code:

   0:	66 0f 3a 44 c8 02    	pclmullqhqdq xmm1,xmm0
   6:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   b:	66 0f db c0          	pand   xmm0,xmm0
   f:	66 0f db c0          	pand   xmm0,xmm0
  13:	66 0f db c0          	pand   xmm0,xmm0
  17:	66 0f db c0          	pand   xmm0,xmm0
  1b:	66 0f db c0          	pand   xmm0,xmm0
  1f:	66 0f db c0          	pand   xmm0,xmm0

Init:

PXOR XMM1, XMM1;
PXOR XMM0, XMM0;
PCLMULQDQ XMM1, XMM0, 2;
PCLMULQDQ XMM0, XMM1, 2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 6.59
- TOPDOWN_RETIRING.ALL: 8.0

PCLMULQDQ (XMM, XMM, I8) - Latency

Operands

Latency operand 1 → 1: 4

Latency operand 2 → 1: 4

Latency operand 1 → 1: 4

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1: 4

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)