VPOR (XMM, XMM, XMM)

Experiment 1

Instruction: VPOR XMM1, XMM0, XMM2
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	c5 f9 eb ca          	vpor   xmm1,xmm0,xmm2
   4:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   9:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   e:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  13:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  18:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 6.01
- UOPS_RETIRED.ALL: 6.0

Experiment 2

Instruction: VPOR XMM1, XMM0, XMM2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	c5 f9 eb ca          	vpor   xmm1,xmm0,xmm2
   4:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   8:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   c:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  10:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  14:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 6.06
- UOPS_RETIRED.ALL: 6.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPOR XMM1, XMM0, XMM2
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	c5 f9 eb ca          	vpor   xmm1,xmm0,xmm2
   4:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   9:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   e:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  13:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  18:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM2, XMM2, XMM2;
VPOR XMM0, XMM1, XMM2;
VPOR XMM2, XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 6.06
- UOPS_RETIRED.ALL: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPOR XMM1, XMM0, XMM2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	c5 f9 eb ca          	vpor   xmm1,xmm0,xmm2
   4:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   8:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   c:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  10:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  14:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM2, XMM2, XMM2;
VPOR XMM0, XMM1, XMM2;
VPOR XMM2, XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 6.06
- UOPS_RETIRED.ALL: 6.0

Experiment 1

Instruction: VPOR XMM1, XMM2, XMM0
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	c5 e9 eb c8          	vpor   xmm1,xmm2,xmm0
   4:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   9:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   e:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  13:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  18:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 6.12
- UOPS_RETIRED.ALL: 6.0

Experiment 2

Instruction: VPOR XMM1, XMM2, XMM0
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	c5 e9 eb c8          	vpor   xmm1,xmm2,xmm0
   4:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   8:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   c:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  10:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  14:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 6.06
- UOPS_RETIRED.ALL: 6.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPOR XMM1, XMM2, XMM0
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	c5 e9 eb c8          	vpor   xmm1,xmm2,xmm0
   4:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   9:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   e:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  13:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  18:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM0, XMM0, XMM0;
VPOR XMM2, XMM0, XMM1;
VPOR XMM0, XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 6.12
- UOPS_RETIRED.ALL: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPOR XMM1, XMM2, XMM0
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	c5 e9 eb c8          	vpor   xmm1,xmm2,xmm0
   4:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   8:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   c:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  10:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  14:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM0, XMM0, XMM0;
VPOR XMM2, XMM0, XMM1;
VPOR XMM0, XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 6.06
- UOPS_RETIRED.ALL: 6.0

VPOR (XMM, XMM, XMM) - Latency

Operands

Latency operand 2 → 1: 1

Latency operand 3 → 1: 1

Latency operand 2 → 1: 1

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 1

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)