PHMINPOSUW (XMM, XMM)

Experiment 1

Instruction: PHMINPOSUW XMM1, XMM0
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	66 0f 38 41 c8       	phminposuw xmm1,xmm0
   5:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  28:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.0
- Reference cycles: 14.0
- UOPS_RETIRED.ALL: 10.0

Experiment 2

Instruction: PHMINPOSUW XMM1, XMM0
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 9

Code:

   0:	66 0f 38 41 c8       	phminposuw xmm1,xmm0
   5:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0
  1a:	66 0f db c0          	pand   xmm0,xmm0
  1e:	66 0f db c0          	pand   xmm0,xmm0
  22:	66 0f db c0          	pand   xmm0,xmm0
  26:	66 0f db c0          	pand   xmm0,xmm0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 16.0
- Reference cycles: 16.04
- UOPS_RETIRED.ALL: 10.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: PHMINPOSUW XMM1, XMM0
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	66 0f 38 41 c8       	phminposuw xmm1,xmm0
   5:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  28:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PHMINPOSUW XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.0
- Reference cycles: 14.0
- UOPS_RETIRED.ALL: 10.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: PHMINPOSUW XMM1, XMM0
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 9

Code:

   0:	66 0f 38 41 c8       	phminposuw xmm1,xmm0
   5:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0
  1a:	66 0f db c0          	pand   xmm0,xmm0
  1e:	66 0f db c0          	pand   xmm0,xmm0
  22:	66 0f db c0          	pand   xmm0,xmm0
  26:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PHMINPOSUW XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 16.0
- Reference cycles: 15.92
- UOPS_RETIRED.ALL: 10.0

Experiment 5 (with the same register for different operands)

Instruction: PHMINPOSUW XMM0, XMM0

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 5.0
- Reference cycles: 5.1
- UOPS_RETIRED.ALL: 1.0

Experiment 6 (with the same register for different operands)

Instruction: PHMINPOSUW XMM0, XMM0
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0
   5:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  28:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.0
- Reference cycles: 14.0
- UOPS_RETIRED.ALL: 10.0

Experiment 7 (with the same register for different operands)

Instruction: PHMINPOSUW XMM0, XMM0
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 9

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0
   5:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0
  1a:	66 0f db c0          	pand   xmm0,xmm0
  1e:	66 0f db c0          	pand   xmm0,xmm0
  22:	66 0f db c0          	pand   xmm0,xmm0
  26:	66 0f db c0          	pand   xmm0,xmm0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 16.0
- Reference cycles: 15.98
- UOPS_RETIRED.ALL: 10.0

Experiment 8 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Instruction: PHMINPOSUW XMM0, XMM0

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PHMINPOSUW XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 5.0
- Reference cycles: 5.1
- UOPS_RETIRED.ALL: 1.0

Experiment 9 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Instruction: PHMINPOSUW XMM0, XMM0
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0
   5:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  28:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PHMINPOSUW XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.0
- Reference cycles: 14.05
- UOPS_RETIRED.ALL: 10.0

Experiment 10 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Instruction: PHMINPOSUW XMM0, XMM0
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 9

Code:

   0:	66 0f 38 41 c0       	phminposuw xmm0,xmm0
   5:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0
  1a:	66 0f db c0          	pand   xmm0,xmm0
  1e:	66 0f db c0          	pand   xmm0,xmm0
  22:	66 0f db c0          	pand   xmm0,xmm0
  26:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PHMINPOSUW XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 16.0
- Reference cycles: 15.92
- UOPS_RETIRED.ALL: 10.0

PHMINPOSUW (XMM, XMM) - Latency

Operands

Latency operand 2 → 1: 5

Latency operand 2 → 1: 5

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (with the same register for different operands)

Experiment 6 (with the same register for different operands)

Experiment 7 (with the same register for different operands)

Experiment 8 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 9 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 10 (source registers initialized by an instruction of the same kind, with the same register for different operands)