PCLMULQDQ (XMM, XMM, I8)

Experiment 1

Instruction: PCLMULQDQ XMM0, XMM1, 2

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 13.39
- Reference cycles: 13.49
- UOPS_RETIRED.ALL: 18.0

Experiment 2

Instruction: PCLMULQDQ XMM0, XMM1, 2
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 17

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   b:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  10:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  15:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  24:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  29:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  33:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  38:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  3d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  42:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  47:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  4c:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  51:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  56:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 30.0
- Reference cycles: 30.03
- UOPS_RETIRED.ALL: 35.0

Experiment 3

Instruction: PCLMULQDQ XMM0, XMM1, 2
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 17

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   b:	66 0f db c0          	pand   xmm0,xmm0
   f:	66 0f db c0          	pand   xmm0,xmm0
  13:	66 0f db c0          	pand   xmm0,xmm0
  17:	66 0f db c0          	pand   xmm0,xmm0
  1b:	66 0f db c0          	pand   xmm0,xmm0
  1f:	66 0f db c0          	pand   xmm0,xmm0
  23:	66 0f db c0          	pand   xmm0,xmm0
  27:	66 0f db c0          	pand   xmm0,xmm0
  2b:	66 0f db c0          	pand   xmm0,xmm0
  2f:	66 0f db c0          	pand   xmm0,xmm0
  33:	66 0f db c0          	pand   xmm0,xmm0
  37:	66 0f db c0          	pand   xmm0,xmm0
  3b:	66 0f db c0          	pand   xmm0,xmm0
  3f:	66 0f db c0          	pand   xmm0,xmm0
  43:	66 0f db c0          	pand   xmm0,xmm0
  47:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 30.74
- Reference cycles: 30.43
- UOPS_RETIRED.ALL: 35.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: PCLMULQDQ XMM0, XMM1, 2

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PCLMULQDQ XMM0, XMM1, 2;
PCLMULQDQ XMM1, XMM0, 2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 13.64
- Reference cycles: 13.71
- UOPS_RETIRED.ALL: 18.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: PCLMULQDQ XMM0, XMM1, 2
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 17

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   b:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  10:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  15:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  24:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  29:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  33:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  38:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  3d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  42:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  47:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  4c:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  51:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  56:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PCLMULQDQ XMM0, XMM1, 2;
PCLMULQDQ XMM1, XMM0, 2

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 30.02
- Reference cycles: 30.26
- UOPS_RETIRED.ALL: 35.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: PCLMULQDQ XMM0, XMM1, 2
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 17

Code:

   0:	66 0f 3a 44 c1 02    	pclmullqhqdq xmm0,xmm1
   6:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   b:	66 0f db c0          	pand   xmm0,xmm0
   f:	66 0f db c0          	pand   xmm0,xmm0
  13:	66 0f db c0          	pand   xmm0,xmm0
  17:	66 0f db c0          	pand   xmm0,xmm0
  1b:	66 0f db c0          	pand   xmm0,xmm0
  1f:	66 0f db c0          	pand   xmm0,xmm0
  23:	66 0f db c0          	pand   xmm0,xmm0
  27:	66 0f db c0          	pand   xmm0,xmm0
  2b:	66 0f db c0          	pand   xmm0,xmm0
  2f:	66 0f db c0          	pand   xmm0,xmm0
  33:	66 0f db c0          	pand   xmm0,xmm0
  37:	66 0f db c0          	pand   xmm0,xmm0
  3b:	66 0f db c0          	pand   xmm0,xmm0
  3f:	66 0f db c0          	pand   xmm0,xmm0
  43:	66 0f db c0          	pand   xmm0,xmm0
  47:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PCLMULQDQ XMM0, XMM1, 2;
PCLMULQDQ XMM1, XMM0, 2

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 30.73
- Reference cycles: 30.77
- UOPS_RETIRED.ALL: 35.0

Experiment 1

Instruction: PCLMULQDQ XMM1, XMM0, 2
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 17

Code:

   0:	66 0f 3a 44 c8 02    	pclmullqhqdq xmm1,xmm0
   6:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   b:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  10:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  15:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  24:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  29:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  33:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  38:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  3d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  42:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  47:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  4c:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  51:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  56:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 31.45
- Reference cycles: 31.56
- UOPS_RETIRED.ALL: 35.0

Experiment 2

Instruction: PCLMULQDQ XMM1, XMM0, 2
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 17

Code:

   0:	66 0f 3a 44 c8 02    	pclmullqhqdq xmm1,xmm0
   6:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   b:	66 0f db c0          	pand   xmm0,xmm0
   f:	66 0f db c0          	pand   xmm0,xmm0
  13:	66 0f db c0          	pand   xmm0,xmm0
  17:	66 0f db c0          	pand   xmm0,xmm0
  1b:	66 0f db c0          	pand   xmm0,xmm0
  1f:	66 0f db c0          	pand   xmm0,xmm0
  23:	66 0f db c0          	pand   xmm0,xmm0
  27:	66 0f db c0          	pand   xmm0,xmm0
  2b:	66 0f db c0          	pand   xmm0,xmm0
  2f:	66 0f db c0          	pand   xmm0,xmm0
  33:	66 0f db c0          	pand   xmm0,xmm0
  37:	66 0f db c0          	pand   xmm0,xmm0
  3b:	66 0f db c0          	pand   xmm0,xmm0
  3f:	66 0f db c0          	pand   xmm0,xmm0
  43:	66 0f db c0          	pand   xmm0,xmm0
  47:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 31.02
- Reference cycles: 30.94
- UOPS_RETIRED.ALL: 35.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: PCLMULQDQ XMM1, XMM0, 2
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 17

Code:

   0:	66 0f 3a 44 c8 02    	pclmullqhqdq xmm1,xmm0
   6:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   b:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  10:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  15:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  24:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  29:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  33:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  38:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  3d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  42:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  47:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  4c:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  51:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  56:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0;
PCLMULQDQ XMM1, XMM0, 2;
PCLMULQDQ XMM0, XMM1, 2

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 31.43
- Reference cycles: 31.45
- UOPS_RETIRED.ALL: 35.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: PCLMULQDQ XMM1, XMM0, 2
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 17

Code:

   0:	66 0f 3a 44 c8 02    	pclmullqhqdq xmm1,xmm0
   6:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   b:	66 0f db c0          	pand   xmm0,xmm0
   f:	66 0f db c0          	pand   xmm0,xmm0
  13:	66 0f db c0          	pand   xmm0,xmm0
  17:	66 0f db c0          	pand   xmm0,xmm0
  1b:	66 0f db c0          	pand   xmm0,xmm0
  1f:	66 0f db c0          	pand   xmm0,xmm0
  23:	66 0f db c0          	pand   xmm0,xmm0
  27:	66 0f db c0          	pand   xmm0,xmm0
  2b:	66 0f db c0          	pand   xmm0,xmm0
  2f:	66 0f db c0          	pand   xmm0,xmm0
  33:	66 0f db c0          	pand   xmm0,xmm0
  37:	66 0f db c0          	pand   xmm0,xmm0
  3b:	66 0f db c0          	pand   xmm0,xmm0
  3f:	66 0f db c0          	pand   xmm0,xmm0
  43:	66 0f db c0          	pand   xmm0,xmm0
  47:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0;
PCLMULQDQ XMM1, XMM0, 2;
PCLMULQDQ XMM0, XMM1, 2

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 30.88
- Reference cycles: 30.94
- UOPS_RETIRED.ALL: 35.0

PCLMULQDQ (XMM, XMM, I8) - Latency

Operands

Latency operand 1 → 1: 13

Latency operand 2 → 1: 14

Latency operand 1 → 1: 13

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1: 14

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)