BSR (R64, M64)

Experiment 1

Instruction: BSR R8, qword ptr [R14]

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.0
- Reference cycles: 3.0
- UOPS_RETIRED.ALL: 2.0

Experiment 2

Instruction: BSR R8, qword ptr [R14]
Chain instructions: MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 7

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 63 c0             	movsxd r8,r8d
   7:	4d 63 c0             	movsxd r8,r8d
   a:	4d 63 c0             	movsxd r8,r8d
   d:	4d 63 c0             	movsxd r8,r8d
  10:	4d 63 c0             	movsxd r8,r8d
  13:	4d 63 c0             	movsxd r8,r8d
  16:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.0
- Reference cycles: 9.97
- UOPS_RETIRED.ALL: 9.0

Latency operand 1 → 3: 3

Experiment 1

Instruction: BSR R8, qword ptr [R14]
Chain instructions: CMOVZ R15, R15;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 9

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 0f 44 ff          	cmove  r15,r15
   8:	4d 63 c7             	movsxd r8,r15d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d
  14:	4d 63 c0             	movsxd r8,r8d
  17:	4d 63 c0             	movsxd r8,r8d
  1a:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 12.0
- Reference cycles: 11.9
- UOPS_RETIRED.ALL: 11.0

Latency operand 2 → 1 (address, base register): 8

Experiment 1

Instruction: BSR R8, qword ptr [R14]
Chain instructions: MOVSX R8, R8D;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8
Chain latency: 7

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 63 c0             	movsxd r8,r8d
   7:	4d 31 c6             	xor    r14,r8
   a:	4d 31 c6             	xor    r14,r8
   d:	4d 31 c6             	xor    r14,r8
  10:	4d 31 c6             	xor    r14,r8
  13:	4d 31 c6             	xor    r14,r8
  16:	4d 31 c6             	xor    r14,r8

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 15.01
- Reference cycles: 15.13
- UOPS_RETIRED.ALL: 9.0

Latency operand 2 → 1 (address, index register): 8

Experiment 1

Instruction: BSR R8, qword ptr [R14+R13]
Chain instructions: MOVSX R8, R8D;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8
Chain latency: 7

Code:

   0:	4f 0f bd 04 2e       	bsr    r8,QWORD PTR [r14+r13*1]
   5:	4d 63 c0             	movsxd r8,r8d
   8:	4d 31 c5             	xor    r13,r8
   b:	4d 31 c5             	xor    r13,r8
   e:	4d 31 c5             	xor    r13,r8
  11:	4d 31 c5             	xor    r13,r8
  14:	4d 31 c5             	xor    r13,r8
  17:	4d 31 c5             	xor    r13,r8

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 15.02
- Reference cycles: 14.96
- UOPS_RETIRED.ALL: 9.0

Latency operand 2 → 1 (memory): ≤7

Experiment 1

Instruction: BSR R8, qword ptr [R14]
Chain instructions: MOVSX R12, R8D;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12
Chain latency: ≥7

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 63 e0             	movsxd r12,r8d
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 89 26             	mov    QWORD PTR [r14],r12

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 14.01
- Reference cycles: 13.94
- UOPS_RETIRED.ALL: 10.0

Latency operand 2 → 3 (address, base register): 8

Experiment 1

Instruction: BSR R8, qword ptr [R14]
Chain instruction: CMOVZ R14, R14
Chain latency: 2

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 0f 44 f6          	cmove  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 10.0
- Reference cycles: 9.92
- UOPS_RETIRED.ALL: 4.0

Latency operand 2 → 3 (address, index register): 8

Experiment 1

Instruction: BSR R8, qword ptr [R14+R13]
Chain instruction: CMOVZ R13, R13
Chain latency: 2

Code:

   0:	4f 0f bd 04 2e       	bsr    r8,QWORD PTR [r14+r13*1]
   5:	4d 0f 44 ed          	cmove  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 10.0
- Reference cycles: 9.97
- UOPS_RETIRED.ALL: 4.0

Latency operand 2 → 3 (memory): ≤7

Experiment 1

Instruction: BSR R8, qword ptr [R14]
Chain instructions: CMOVZ R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12
Chain latency: ≥9

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 0f 44 e4          	cmove  r12,r12
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 89 26             	mov    QWORD PTR [r14],r12

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 16.0
- Reference cycles: 15.92
- UOPS_RETIRED.ALL: 12.0

BSR (R64, M64) - Latency

Operands

Latency operand 1 → 1: 3

Latency operand 1 → 3: 3

Latency operand 2 → 1 (address, base register): 8

Latency operand 2 → 1 (address, index register): 8

Latency operand 2 → 1 (memory): ≤7

Latency operand 2 → 3 (address, base register): 8

Latency operand 2 → 3 (address, index register): 8

Latency operand 2 → 3 (memory): ≤7

Latency operand 1 → 1: 3

Experiment 1

Experiment 2

Latency operand 1 → 3: 3

Experiment 1

Latency operand 2 → 1 (address, base register): 8

Experiment 1

Latency operand 2 → 1 (address, index register): 8

Experiment 1

Latency operand 2 → 1 (memory): ≤7

Experiment 1

Latency operand 2 → 3 (address, base register): 8

Experiment 1

Latency operand 2 → 3 (address, index register): 8

Experiment 1

Latency operand 2 → 3 (memory): ≤7

Experiment 1