VPCMPEQB (YMM, YMM, YMM)

Experiment 1

Instruction: VPCMPEQB YMM1, YMM0, YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c5 fd 74 ca          	vpcmpeqb ymm1,ymm0,ymm2
   4:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   9:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  13:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  18:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.38
- UOPS_EXECUTED.THREAD: 6.0

Experiment 2

Instruction: VPCMPEQB YMM1, YMM0, YMM2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c5 fd 74 ca          	vpcmpeqb ymm1,ymm0,ymm2
   4:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   8:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   c:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  10:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  14:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.62
- UOPS_EXECUTED.THREAD: 6.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPCMPEQB YMM1, YMM0, YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c5 fd 74 ca          	vpcmpeqb ymm1,ymm0,ymm2
   4:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   9:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  13:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  18:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2;
VPCMPEQB YMM0, YMM1, YMM2;
VPCMPEQB YMM2, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.62
- UOPS_EXECUTED.THREAD: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPCMPEQB YMM1, YMM0, YMM2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c5 fd 74 ca          	vpcmpeqb ymm1,ymm0,ymm2
   4:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   8:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   c:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  10:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  14:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2;
VPCMPEQB YMM0, YMM1, YMM2;
VPCMPEQB YMM2, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.01
- Reference cycles: 5.35
- UOPS_EXECUTED.THREAD: 6.0

Experiment 1

Instruction: VPCMPEQB YMM1, YMM2, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c5 ed 74 c8          	vpcmpeqb ymm1,ymm2,ymm0
   4:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   9:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  13:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  18:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 6.08
- UOPS_EXECUTED.THREAD: 6.0

Experiment 2

Instruction: VPCMPEQB YMM1, YMM2, YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c5 ed 74 c8          	vpcmpeqb ymm1,ymm2,ymm0
   4:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   8:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   c:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  10:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  14:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.01
- Reference cycles: 5.84
- UOPS_EXECUTED.THREAD: 6.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPCMPEQB YMM1, YMM2, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c5 ed 74 c8          	vpcmpeqb ymm1,ymm2,ymm0
   4:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   9:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  13:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  18:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0;
VPCMPEQB YMM2, YMM0, YMM1;
VPCMPEQB YMM0, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 5.35
- UOPS_EXECUTED.THREAD: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPCMPEQB YMM1, YMM2, YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c5 ed 74 c8          	vpcmpeqb ymm1,ymm2,ymm0
   4:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   8:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   c:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  10:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  14:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0;
VPCMPEQB YMM2, YMM0, YMM1;
VPCMPEQB YMM0, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.87
- UOPS_EXECUTED.THREAD: 6.0

VPCMPEQB (YMM, YMM, YMM) - Latency

Operands

Latency operand 2 → 1: 1

Latency operand 3 → 1: 1

Latency operand 2 → 1: 1

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 1

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)