VFMADD132PS (YMM, YMM, YMM)

Experiment 1

Instruction: VFMADD132PS YMM0, YMM1, YMM2

Code:

   0:	c4 e2 75 98 c2       	vfmadd132ps ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 3.41
- UOPS_EXECUTED.THREAD: 1.0

Experiment 2

Instruction: VFMADD132PS YMM0, YMM1, YMM2
Chain instructions: VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 e2 75 98 c2       	vfmadd132ps ymm0,ymm1,ymm2
   5:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  23:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 9.25
- UOPS_EXECUTED.THREAD: 8.0

Experiment 3

Instruction: VFMADD132PS YMM0, YMM1, YMM2
Chain instructions: VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 7

Code:

   0:	c4 e2 75 98 c2       	vfmadd132ps ymm0,ymm1,ymm2
   5:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  19:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.89
- Reference cycles: 11.68
- UOPS_EXECUTED.THREAD: 8.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD132PS YMM0, YMM1, YMM2

Code:

   0:	c4 e2 75 98 c2       	vfmadd132ps ymm0,ymm1,ymm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VFMADD132PS YMM0, YMM1, YMM2;
VFMADD132PS YMM1, YMM0, YMM2;
VFMADD132PS YMM2, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 3.41
- UOPS_EXECUTED.THREAD: 1.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD132PS YMM0, YMM1, YMM2
Chain instructions: VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 e2 75 98 c2       	vfmadd132ps ymm0,ymm1,ymm2
   5:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  23:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VFMADD132PS YMM0, YMM1, YMM2;
VFMADD132PS YMM1, YMM0, YMM2;
VFMADD132PS YMM2, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 9.25
- UOPS_EXECUTED.THREAD: 8.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD132PS YMM0, YMM1, YMM2
Chain instructions: VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 7

Code:

   0:	c4 e2 75 98 c2       	vfmadd132ps ymm0,ymm1,ymm2
   5:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  19:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VFMADD132PS YMM0, YMM1, YMM2;
VFMADD132PS YMM1, YMM0, YMM2;
VFMADD132PS YMM2, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.89
- Reference cycles: 11.68
- UOPS_EXECUTED.THREAD: 8.0

Latency operand 2 → 1: 4

Experiment 1

Instruction: VFMADD132PS YMM1, YMM0, YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 e2 7d 98 ca       	vfmadd132ps ymm1,ymm0,ymm2
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  23:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 9.98
- UOPS_EXECUTED.THREAD: 8.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VFMADD132PS YMM1, YMM0, YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;;VMOVUPD YMM1, YMM15
Chain latency: 7

Code:

   0:	c4 e2 7d 98 ca       	vfmadd132ps ymm1,ymm0,ymm2
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  23:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  28:	c5 7d 11 f9          	vmovupd ymm1,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.0
- Reference cycles: 9.73
- UOPS_EXECUTED.THREAD: 8.0

Experiment 3

Instruction: VFMADD132PS YMM1, YMM0, YMM2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 7

Code:

   0:	c4 e2 7d 98 ca       	vfmadd132ps ymm1,ymm0,ymm2
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  19:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.75
- Reference cycles: 11.68
- UOPS_EXECUTED.THREAD: 8.0

Experiment 4 (with dependency-breaking instructions)

Instruction: VFMADD132PS YMM1, YMM0, YMM2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;;VMOVUPD YMM1, YMM15
Chain latency: 7

Code:

   0:	c4 e2 7d 98 ca       	vfmadd132ps ymm1,ymm0,ymm2
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  19:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  21:	c5 7d 11 f9          	vmovupd ymm1,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 12.56
- Reference cycles: 11.44
- UOPS_EXECUTED.THREAD: 8.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD132PS YMM1, YMM0, YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 e2 7d 98 ca       	vfmadd132ps ymm1,ymm0,ymm2
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  23:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14];
VFMADD132PS YMM1, YMM0, YMM2;
VFMADD132PS YMM0, YMM1, YMM2;
VFMADD132PS YMM2, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 9.73
- UOPS_EXECUTED.THREAD: 8.0

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VFMADD132PS YMM1, YMM0, YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;;VMOVUPD YMM1, YMM15
Chain latency: 7

Code:

   0:	c4 e2 7d 98 ca       	vfmadd132ps ymm1,ymm0,ymm2
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  23:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  28:	c5 7d 11 f9          	vmovupd ymm1,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14];
VFMADD132PS YMM1, YMM0, YMM2;
VFMADD132PS YMM0, YMM1, YMM2;
VFMADD132PS YMM2, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.0
- Reference cycles: 9.73
- UOPS_EXECUTED.THREAD: 8.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD132PS YMM1, YMM0, YMM2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 7

Code:

   0:	c4 e2 7d 98 ca       	vfmadd132ps ymm1,ymm0,ymm2
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  19:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14];
VFMADD132PS YMM1, YMM0, YMM2;
VFMADD132PS YMM0, YMM1, YMM2;
VFMADD132PS YMM2, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.87
- Reference cycles: 11.68
- UOPS_EXECUTED.THREAD: 8.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VFMADD132PS YMM1, YMM0, YMM2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;;VMOVUPD YMM1, YMM15
Chain latency: 7

Code:

   0:	c4 e2 7d 98 ca       	vfmadd132ps ymm1,ymm0,ymm2
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  19:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  21:	c5 7d 11 f9          	vmovupd ymm1,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14];
VFMADD132PS YMM1, YMM0, YMM2;
VFMADD132PS YMM0, YMM1, YMM2;
VFMADD132PS YMM2, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 12.56
- Reference cycles: 11.68
- UOPS_EXECUTED.THREAD: 8.0

Latency operand 3 → 1: 4

Experiment 1

Instruction: VFMADD132PS YMM1, YMM2, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 e2 6d 98 c8       	vfmadd132ps ymm1,ymm2,ymm0
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  23:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 9.73
- UOPS_EXECUTED.THREAD: 8.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VFMADD132PS YMM1, YMM2, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;;VMOVUPD YMM1, YMM15
Chain latency: 7

Code:

   0:	c4 e2 6d 98 c8       	vfmadd132ps ymm1,ymm2,ymm0
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  23:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  28:	c5 7d 11 f9          	vmovupd ymm1,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.0
- Reference cycles: 9.73
- UOPS_EXECUTED.THREAD: 8.0

Experiment 3

Instruction: VFMADD132PS YMM1, YMM2, YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 7

Code:

   0:	c4 e2 6d 98 c8       	vfmadd132ps ymm1,ymm2,ymm0
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  19:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.71
- Reference cycles: 11.68
- UOPS_EXECUTED.THREAD: 8.0

Experiment 4 (with dependency-breaking instructions)

Instruction: VFMADD132PS YMM1, YMM2, YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;;VMOVUPD YMM1, YMM15
Chain latency: 7

Code:

   0:	c4 e2 6d 98 c8       	vfmadd132ps ymm1,ymm2,ymm0
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  19:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  21:	c5 7d 11 f9          	vmovupd ymm1,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 12.56
- Reference cycles: 10.95
- UOPS_EXECUTED.THREAD: 8.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD132PS YMM1, YMM2, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 e2 6d 98 c8       	vfmadd132ps ymm1,ymm2,ymm0
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  23:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14];
VFMADD132PS YMM1, YMM0, YMM2;
VFMADD132PS YMM2, YMM0, YMM1;
VFMADD132PS YMM0, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 9.98
- UOPS_EXECUTED.THREAD: 8.0

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VFMADD132PS YMM1, YMM2, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;;VMOVUPD YMM1, YMM15
Chain latency: 7

Code:

   0:	c4 e2 6d 98 c8       	vfmadd132ps ymm1,ymm2,ymm0
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  23:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  28:	c5 7d 11 f9          	vmovupd ymm1,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14];
VFMADD132PS YMM1, YMM0, YMM2;
VFMADD132PS YMM2, YMM0, YMM1;
VFMADD132PS YMM0, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.0
- Reference cycles: 10.22
- UOPS_EXECUTED.THREAD: 8.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD132PS YMM1, YMM2, YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 7

Code:

   0:	c4 e2 6d 98 c8       	vfmadd132ps ymm1,ymm2,ymm0
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  19:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14];
VFMADD132PS YMM1, YMM0, YMM2;
VFMADD132PS YMM2, YMM0, YMM1;
VFMADD132PS YMM0, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.75
- Reference cycles: 11.68
- UOPS_EXECUTED.THREAD: 8.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VFMADD132PS YMM1, YMM2, YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;;VMOVUPD YMM1, YMM15
Chain latency: 7

Code:

   0:	c4 e2 6d 98 c8       	vfmadd132ps ymm1,ymm2,ymm0
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  19:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  21:	c5 7d 11 f9          	vmovupd ymm1,ymm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14];
VFMADD132PS YMM1, YMM0, YMM2;
VFMADD132PS YMM2, YMM0, YMM1;
VFMADD132PS YMM0, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 12.68
- Reference cycles: 11.68
- UOPS_EXECUTED.THREAD: 8.0

VFMADD132PS (YMM, YMM, YMM) - Latency

Operands

Latency operand 1 → 1: 4

Latency operand 2 → 1: 4

Latency operand 3 → 1: 4

Latency operand 1 → 1: 4

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1: 4

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Latency operand 3 → 1: 4

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)