VGATHERDPS (YMM, VSIB

Experiment 1

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instruction: VPCMPEQD YMM1, YMM1, YMM1

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 5.0
- Reference cycles: 4.66
- UOPS_EXECUTED.THREAD: 6.0

Experiment 2

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instructions: VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: 9

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.0
- Reference cycles: 8.42
- UOPS_EXECUTED.THREAD: 15.0

Experiment 3

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instructions: VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: 9

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.01
- Reference cycles: 9.09
- UOPS_EXECUTED.THREAD: 15.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instruction: VPCMPEQD YMM1, YMM1, YMM1

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM0, [R14+YMM14], YMM1;
VGATHERDPS YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 5.0
- Reference cycles: 4.66
- UOPS_EXECUTED.THREAD: 6.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instructions: VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: 9

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM0, [R14+YMM14], YMM1;
VGATHERDPS YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.0
- Reference cycles: 8.65
- UOPS_EXECUTED.THREAD: 15.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instructions: VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: 9

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM0, [R14+YMM14], YMM1;
VGATHERDPS YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.0
- Reference cycles: 8.65
- UOPS_EXECUTED.THREAD: 15.0

Latency operand 1 → 3: 0

Experiment 1

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: 9

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.0
- Reference cycles: 8.87
- UOPS_EXECUTED.THREAD: 15.0

Experiment 2

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: 9

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 6.0
- Reference cycles: 5.32
- UOPS_EXECUTED.THREAD: 15.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: 9

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM0, [R14+YMM14], YMM1;
VGATHERDPS YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.0
- Reference cycles: 8.65
- UOPS_EXECUTED.THREAD: 15.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: 9

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM0, [R14+YMM14], YMM1;
VGATHERDPS YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 6.0
- Reference cycles: 5.32
- UOPS_EXECUTED.THREAD: 15.0

Latency operand 2 → 1 (address, base register): ≤18

Experiment 1

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: ≥9

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12
  1d:	4d 31 e6             	xor    r14,r12
  20:	4d 31 e6             	xor    r14,r12
  23:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 27.0
- Reference cycles: 23.94
- UOPS_EXECUTED.THREAD: 15.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: ≥9

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12
  1d:	4d 31 e6             	xor    r14,r12
  20:	4d 31 e6             	xor    r14,r12
  23:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM0, [R14+YMM14], YMM1;
VGATHERDPS YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 27.0
- Reference cycles: 23.94
- UOPS_EXECUTED.THREAD: 15.0

Latency operand 2 → 1 (address, index register): ≤22

Experiment 1

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instructions: VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: ≥8

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   a:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   e:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  12:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  16:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1a:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1e:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  22:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  26:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 30.01
- Reference cycles: 26.6
- UOPS_EXECUTED.THREAD: 14.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instructions: VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: ≥8

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   a:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   e:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  12:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  16:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1a:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1e:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  22:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  26:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM0, [R14+YMM14], YMM1;
VGATHERDPS YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 30.0
- Reference cycles: 26.6
- UOPS_EXECUTED.THREAD: 14.0

Latency operand 2 → 1 (memory): ≤15

Experiment 1

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instructions: VSHUFPD XMM13, XMM0, XMM0, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VMOVSS [R14], XMM13;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: ≥10

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c5 79 c6 e8 00       	vshufpd xmm13,xmm0,xmm0,0x0
   b:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  11:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  17:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  1d:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  23:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  29:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  2f:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  35:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  3b:	c4 41 7a 11 2e       	vmovss DWORD PTR [r14],xmm13
  40:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 25.0
- Reference cycles: 22.83
- UOPS_EXECUTED.THREAD: 17.0

Experiment 2

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instructions: VPAND XMM13, XMM0, XMM0;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VMOVD [R14], XMM13;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: ≥10

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c5 79 db e8          	vpand  xmm13,xmm0,xmm0
   a:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
   f:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  14:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  19:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  1e:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  23:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  28:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  2d:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  32:	c4 41 79 7e 2e       	vmovd  DWORD PTR [r14],xmm13
  37:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 25.0
- Reference cycles: 21.95
- UOPS_EXECUTED.THREAD: 17.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instructions: VSHUFPD XMM13, XMM0, XMM0, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VMOVSS [R14], XMM13;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: ≥10

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c5 79 c6 e8 00       	vshufpd xmm13,xmm0,xmm0,0x0
   b:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  11:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  17:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  1d:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  23:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  29:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  2f:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  35:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  3b:	c4 41 7a 11 2e       	vmovss DWORD PTR [r14],xmm13
  40:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM0, [R14+YMM14], YMM1;
VGATHERDPS YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 25.0
- Reference cycles: 21.28
- UOPS_EXECUTED.THREAD: 17.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM0, [R14+YMM14], YMM1
Chain instructions: VPAND XMM13, XMM0, XMM0;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VMOVD [R14], XMM13;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: ≥10

Code:

   0:	c4 82 75 92 04 36    	vgatherdps ymm0,DWORD PTR [r14+ymm14*1],ymm1
   6:	c5 79 db e8          	vpand  xmm13,xmm0,xmm0
   a:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
   f:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  14:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  19:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  1e:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  23:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  28:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  2d:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  32:	c4 41 79 7e 2e       	vmovd  DWORD PTR [r14],xmm13
  37:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM0, [R14+YMM14], YMM1;
VGATHERDPS YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 25.0
- Reference cycles: 22.83
- UOPS_EXECUTED.THREAD: 17.0

Latency operand 2 → 3 (address, base register): ≤0

Experiment 1

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;VPCMPEQD YMM0, YMM0, YMM0
Chain latency: ≥9

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12
  1d:	4d 31 e6             	xor    r14,r12
  20:	4d 31 e6             	xor    r14,r12
  23:	c5 fd 76 c0          	vpcmpeqd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 8.24
- Reference cycles: 7.32
- UOPS_EXECUTED.THREAD: 15.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;VPCMPEQD YMM0, YMM0, YMM0
Chain latency: ≥9

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12
  1d:	4d 31 e6             	xor    r14,r12
  20:	4d 31 e6             	xor    r14,r12
  23:	c5 fd 76 c0          	vpcmpeqd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM1, [R14+YMM14], YMM0;
VGATHERDPS YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 8.5
- Reference cycles: 7.09
- UOPS_EXECUTED.THREAD: 15.0

Latency operand 2 → 3 (address, index register): ≤1

Experiment 1

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VPCMPEQD YMM0, YMM0, YMM0
Chain latency: ≥8

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   a:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   e:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  12:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  16:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1a:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1e:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  22:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  26:	c5 fd 76 c0          	vpcmpeqd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.8
- Reference cycles: 7.98
- UOPS_EXECUTED.THREAD: 14.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VPCMPEQD YMM0, YMM0, YMM0
Chain latency: ≥8

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   a:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   e:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  12:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  16:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1a:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1e:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  22:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  26:	c5 fd 76 c0          	vpcmpeqd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM1, [R14+YMM14], YMM0;
VGATHERDPS YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.81
- Reference cycles: 7.98
- UOPS_EXECUTED.THREAD: 14.0

Latency operand 2 → 3 (memory): ≤0

Experiment 1

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VSHUFPD XMM13, XMM0, XMM0, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VMOVSS [R14], XMM13;VPCMPEQD YMM0, YMM0, YMM0
Chain latency: ≥10

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c5 79 c6 e8 00       	vshufpd xmm13,xmm0,xmm0,0x0
   b:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  11:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  17:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  1d:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  23:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  29:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  2f:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  35:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  3b:	c4 41 7a 11 2e       	vmovss DWORD PTR [r14],xmm13
  40:	c5 fd 76 c0          	vpcmpeqd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 10.0
- Reference cycles: 9.09
- UOPS_EXECUTED.THREAD: 17.0

Experiment 2

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VPAND XMM13, XMM0, XMM0;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VMOVD [R14], XMM13;VPCMPEQD YMM0, YMM0, YMM0
Chain latency: ≥10

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c5 79 db e8          	vpand  xmm13,xmm0,xmm0
   a:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
   f:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  14:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  19:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  1e:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  23:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  28:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  2d:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  32:	c4 41 79 7e 2e       	vmovd  DWORD PTR [r14],xmm13
  37:	c5 fd 76 c0          	vpcmpeqd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 6.0
- Reference cycles: 5.32
- UOPS_EXECUTED.THREAD: 17.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VSHUFPD XMM13, XMM0, XMM0, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VMOVSS [R14], XMM13;VPCMPEQD YMM0, YMM0, YMM0
Chain latency: ≥10

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c5 79 c6 e8 00       	vshufpd xmm13,xmm0,xmm0,0x0
   b:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  11:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  17:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  1d:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  23:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  29:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  2f:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  35:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  3b:	c4 41 7a 11 2e       	vmovss DWORD PTR [r14],xmm13
  40:	c5 fd 76 c0          	vpcmpeqd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM1, [R14+YMM14], YMM0;
VGATHERDPS YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 10.0
- Reference cycles: 8.2
- UOPS_EXECUTED.THREAD: 17.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VPAND XMM13, XMM0, XMM0;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VMOVD [R14], XMM13;VPCMPEQD YMM0, YMM0, YMM0
Chain latency: ≥10

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c5 79 db e8          	vpand  xmm13,xmm0,xmm0
   a:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
   f:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  14:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  19:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  1e:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  23:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  28:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  2d:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  32:	c4 41 79 7e 2e       	vmovd  DWORD PTR [r14],xmm13
  37:	c5 fd 76 c0          	vpcmpeqd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM1, [R14+YMM14], YMM0;
VGATHERDPS YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 6.0
- Reference cycles: 5.32
- UOPS_EXECUTED.THREAD: 17.0

Latency operand 3 → 1: 22

Experiment 1

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VPCMPEQD YMM13, YMM13, YMM13;VORPD YMM0, YMM0, YMM13
Chain latency: 10

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
  38:	c4 c1 7d 56 c5       	vorpd  ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 32.0
- Reference cycles: 28.82
- UOPS_EXECUTED.THREAD: 16.0

Experiment 2

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPCMPEQD YMM13, YMM13, YMM13;VPOR YMM0, YMM0, YMM13
Chain latency: 10

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
  2f:	c4 c1 7d eb c5       	vpor   ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 32.0
- Reference cycles: 28.6
- UOPS_EXECUTED.THREAD: 16.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VPCMPEQD YMM13, YMM13, YMM13;VORPD YMM0, YMM0, YMM13
Chain latency: 10

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
  38:	c4 c1 7d 56 c5       	vorpd  ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM1, [R14+YMM14], YMM0;
VGATHERDPS YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 32.0
- Reference cycles: 28.15
- UOPS_EXECUTED.THREAD: 16.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPCMPEQD YMM13, YMM13, YMM13;VPOR YMM0, YMM0, YMM13
Chain latency: 10

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
  2f:	c4 c1 7d eb c5       	vpor   ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM1, [R14+YMM14], YMM0;
VGATHERDPS YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 32.0
- Reference cycles: 28.82
- UOPS_EXECUTED.THREAD: 16.0

Latency operand 3 → 3: 0

Experiment 1

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VPCMPEQD YMM13, YMM13, YMM13;VPOR YMM0, YMM0, YMM13
Chain latency: 1

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
   b:	c4 c1 7d eb c5       	vpor   ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 5.0
- Reference cycles: 5.1
- UOPS_EXECUTED.THREAD: 7.0

Experiment 2

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VPCMPEQD YMM13, YMM13, YMM13;VORPD YMM0, YMM0, YMM13
Chain latency: 10

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
  38:	c4 c1 7d 56 c5       	vorpd  ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 10.0
- Reference cycles: 8.2
- UOPS_EXECUTED.THREAD: 16.0

Experiment 3

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPCMPEQD YMM13, YMM13, YMM13;VPOR YMM0, YMM0, YMM13
Chain latency: 10

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
  2f:	c4 c1 7d eb c5       	vpor   ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 6.0
- Reference cycles: 5.32
- UOPS_EXECUTED.THREAD: 16.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VPCMPEQD YMM13, YMM13, YMM13;VPOR YMM0, YMM0, YMM13
Chain latency: 1

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
   b:	c4 c1 7d eb c5       	vpor   ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM1, [R14+YMM14], YMM0;
VGATHERDPS YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 5.0
- Reference cycles: 4.21
- UOPS_EXECUTED.THREAD: 7.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VPCMPEQD YMM13, YMM13, YMM13;VORPD YMM0, YMM0, YMM13
Chain latency: 10

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  2e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  33:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
  38:	c4 c1 7d 56 c5       	vorpd  ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM1, [R14+YMM14], YMM0;
VGATHERDPS YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 10.0
- Reference cycles: 8.65
- UOPS_EXECUTED.THREAD: 16.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPS YMM1, [R14+YMM14], YMM0
Chain instructions: VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPCMPEQD YMM13, YMM13, YMM13;VPOR YMM0, YMM0, YMM13
Chain latency: 10

Code:

   0:	c4 82 7d 92 0c 36    	vgatherdps ymm1,DWORD PTR [r14+ymm14*1],ymm0
   6:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  26:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  2a:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
  2f:	c4 c1 7d eb c5       	vpor   ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERDPS YMM1, [R14+YMM14], YMM0;
VGATHERDPS YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 6.0
- Reference cycles: 5.1
- UOPS_EXECUTED.THREAD: 16.0

VGATHERDPS (YMM, VSIB_YMM, YMM) - Latency

Operands

Latency operand 1 → 1: 1

Latency operand 1 → 3: 0

Latency operand 2 → 1 (address, base register): ≤18

Latency operand 2 → 1 (address, index register): ≤22

Latency operand 2 → 1 (memory): ≤15

Latency operand 2 → 3 (address, base register): ≤0

Latency operand 2 → 3 (address, index register): ≤1

Latency operand 2 → 3 (memory): ≤0

Latency operand 3 → 1: 22

Latency operand 3 → 3: 0

Latency operand 1 → 1: 1

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 1 → 3: 0

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1 (address, base register): ≤18

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1 (address, index register): ≤22

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1 (memory): ≤15

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 3 (address, base register): ≤0

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 3 (address, index register): ≤1

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 3 (memory): ≤0

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 22

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 3: 0

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)