PCMPEQB (XMM, M128)

Experiment 1

Instruction: PCMPEQB XMM0, xmmword ptr [R14]

Code:

   0:	66 41 0f 74 06       	pcmpeqb xmm0,XMMWORD PTR [r14]

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.89
- UOPS_EXECUTED.THREAD: 2.0

Experiment 2

Instruction: PCMPEQB XMM0, xmmword ptr [R14]
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	66 41 0f 74 06       	pcmpeqb xmm0,XMMWORD PTR [r14]
   5:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 5.32
- UOPS_EXECUTED.THREAD: 7.0

Experiment 3

Instruction: PCMPEQB XMM0, xmmword ptr [R14]
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	66 41 0f 74 06       	pcmpeqb xmm0,XMMWORD PTR [r14]
   5:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 5.32
- UOPS_EXECUTED.THREAD: 7.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: PCMPEQB XMM0, xmmword ptr [R14]

Code:

   0:	66 41 0f 74 06       	pcmpeqb xmm0,XMMWORD PTR [r14]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PCMPEQB XMM0, xmmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.22
- UOPS_EXECUTED.THREAD: 2.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: PCMPEQB XMM0, xmmword ptr [R14]
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	66 41 0f 74 06       	pcmpeqb xmm0,XMMWORD PTR [r14]
   5:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PCMPEQB XMM0, xmmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.1
- Reference cycles: 5.32
- UOPS_EXECUTED.THREAD: 7.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: PCMPEQB XMM0, xmmword ptr [R14]
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	66 41 0f 74 06       	pcmpeqb xmm0,XMMWORD PTR [r14]
   5:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PCMPEQB XMM0, xmmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 5.32
- UOPS_EXECUTED.THREAD: 7.0

Latency operand 2 → 1 (address, base register): ≤8

Experiment 1

Instruction: PCMPEQB XMM0, xmmword ptr [R14]
Chain instructions: MOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥5

Code:

   0:	66 41 0f 74 06       	pcmpeqb xmm0,XMMWORD PTR [r14]
   5:	66 49 0f 7e c4       	movq   r12,xmm0
   a:	4d 31 e6             	xor    r14,r12
   d:	4d 31 e6             	xor    r14,r12
  10:	4d 31 e6             	xor    r14,r12
  13:	4d 31 e6             	xor    r14,r12

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 13.0
- Reference cycles: 11.31
- UOPS_EXECUTED.THREAD: 7.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: PCMPEQB XMM0, xmmword ptr [R14]
Chain instructions: MOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥5

Code:

   0:	66 41 0f 74 06       	pcmpeqb xmm0,XMMWORD PTR [r14]
   5:	66 49 0f 7e c4       	movq   r12,xmm0
   a:	4d 31 e6             	xor    r14,r12
   d:	4d 31 e6             	xor    r14,r12
  10:	4d 31 e6             	xor    r14,r12
  13:	4d 31 e6             	xor    r14,r12

Init:

VZEROALL;
PXOR XMM0, XMM0;
PCMPEQB XMM0, xmmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 13.0
- Reference cycles: 11.08
- UOPS_EXECUTED.THREAD: 7.0

Latency operand 2 → 1 (address, index register): ≤8

Experiment 1

Instruction: PCMPEQB XMM0, xmmword ptr [R14+R13]
Chain instructions: MOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥5

Code:

   0:	66 43 0f 74 04 2e    	pcmpeqb xmm0,XMMWORD PTR [r14+r13*1]
   6:	66 49 0f 7e c4       	movq   r12,xmm0
   b:	4d 31 e5             	xor    r13,r12
   e:	4d 31 e5             	xor    r13,r12
  11:	4d 31 e5             	xor    r13,r12
  14:	4d 31 e5             	xor    r13,r12

Init:
```
VZEROALL;
PXOR XMM0, XMM0;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 13.0
- Reference cycles: 11.75
- UOPS_EXECUTED.THREAD: 7.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: PCMPEQB XMM0, xmmword ptr [R14+R13]
Chain instructions: MOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥5

Code:

   0:	66 43 0f 74 04 2e    	pcmpeqb xmm0,XMMWORD PTR [r14+r13*1]
   6:	66 49 0f 7e c4       	movq   r12,xmm0
   b:	4d 31 e5             	xor    r13,r12
   e:	4d 31 e5             	xor    r13,r12
  11:	4d 31 e5             	xor    r13,r12
  14:	4d 31 e5             	xor    r13,r12

Init:

VZEROALL;
PXOR XMM0, XMM0;
XOR R13, R13;
PCMPEQB XMM0, xmmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 13.0
- Reference cycles: 11.31
- UOPS_EXECUTED.THREAD: 7.0

Latency operand 2 → 1 (memory): ≤5

Experiment 1

Instruction: PCMPEQB XMM0, xmmword ptr [R14]
Chain instructions: SHUFPD XMM13, XMM0, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;MOVUPD [R14], XMM13
Chain latency: ≥6

Code:

   0:	66 41 0f 74 06       	pcmpeqb xmm0,XMMWORD PTR [r14]
   5:	66 44 0f c6 e8 00    	shufpd xmm13,xmm0,0x0
   b:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  11:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  17:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  1d:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  23:	66 45 0f 11 2e       	movupd XMMWORD PTR [r14],xmm13

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 11.0
- Reference cycles: 9.31
- UOPS_EXECUTED.THREAD: 9.0

Experiment 2

Instruction: PCMPEQB XMM0, xmmword ptr [R14]
Chain instructions: PSHUFD XMM13, XMM0, 0;PAND XMM13, XMM13;PAND XMM13, XMM13;PAND XMM13, XMM13;PAND XMM13, XMM13;MOVDQU [R14], XMM13
Chain latency: ≥6

Code:

   0:	66 41 0f 74 06       	pcmpeqb xmm0,XMMWORD PTR [r14]
   5:	66 44 0f 70 e8 00    	pshufd xmm13,xmm0,0x0
   b:	66 45 0f db ed       	pand   xmm13,xmm13
  10:	66 45 0f db ed       	pand   xmm13,xmm13
  15:	66 45 0f db ed       	pand   xmm13,xmm13
  1a:	66 45 0f db ed       	pand   xmm13,xmm13
  1f:	f3 45 0f 7f 2e       	movdqu XMMWORD PTR [r14],xmm13

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 11.01
- Reference cycles: 10.64
- UOPS_EXECUTED.THREAD: 9.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: PCMPEQB XMM0, xmmword ptr [R14]
Chain instructions: SHUFPD XMM13, XMM0, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;MOVUPD [R14], XMM13
Chain latency: ≥6

Code:

   0:	66 41 0f 74 06       	pcmpeqb xmm0,XMMWORD PTR [r14]
   5:	66 44 0f c6 e8 00    	shufpd xmm13,xmm0,0x0
   b:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  11:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  17:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  1d:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  23:	66 45 0f 11 2e       	movupd XMMWORD PTR [r14],xmm13

Init:

VZEROALL;
PXOR XMM0, XMM0;
PCMPEQB XMM0, xmmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 11.01
- Reference cycles: 9.31
- UOPS_EXECUTED.THREAD: 9.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: PCMPEQB XMM0, xmmword ptr [R14]
Chain instructions: PSHUFD XMM13, XMM0, 0;PAND XMM13, XMM13;PAND XMM13, XMM13;PAND XMM13, XMM13;PAND XMM13, XMM13;MOVDQU [R14], XMM13
Chain latency: ≥6

Code:

   0:	66 41 0f 74 06       	pcmpeqb xmm0,XMMWORD PTR [r14]
   5:	66 44 0f 70 e8 00    	pshufd xmm13,xmm0,0x0
   b:	66 45 0f db ed       	pand   xmm13,xmm13
  10:	66 45 0f db ed       	pand   xmm13,xmm13
  15:	66 45 0f db ed       	pand   xmm13,xmm13
  1a:	66 45 0f db ed       	pand   xmm13,xmm13
  1f:	f3 45 0f 7f 2e       	movdqu XMMWORD PTR [r14],xmm13

Init:

VZEROALL;
PXOR XMM0, XMM0;
PCMPEQB XMM0, xmmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 11.11
- Reference cycles: 9.31
- UOPS_EXECUTED.THREAD: 9.0

PCMPEQB (XMM, M128) - Latency

Operands

Latency operand 1 → 1: 1

Latency operand 2 → 1 (address, base register): ≤8

Latency operand 2 → 1 (address, index register): ≤8

Latency operand 2 → 1 (memory): ≤5

Latency operand 1 → 1: 1

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1 (address, base register): ≤8

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1 (address, index register): ≤8

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1 (memory): ≤5

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)