VPSLLVQ (YMM, YMM, YMM)

Experiment 1

Instruction: VPSLLVQ YMM1, YMM0, YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c4 e2 fd 47 ca       	vpsllvq ymm1,ymm0,ymm2
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 5.99
- Reference cycles: 2.95
- UOPS_EXECUTED.THREAD: 6.0

Experiment 2

Instruction: VPSLLVQ YMM1, YMM0, YMM2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 e2 fd 47 ca       	vpsllvq ymm1,ymm0,ymm2
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 2.6
- UOPS_EXECUTED.THREAD: 6.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPSLLVQ YMM1, YMM0, YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c4 e2 fd 47 ca       	vpsllvq ymm1,ymm0,ymm2
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2;
VPSLLVQ YMM0, YMM1, YMM2;
VPSLLVQ YMM2, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 5.99
- Reference cycles: 2.43
- UOPS_EXECUTED.THREAD: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPSLLVQ YMM1, YMM0, YMM2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 e2 fd 47 ca       	vpsllvq ymm1,ymm0,ymm2
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2;
VPSLLVQ YMM0, YMM1, YMM2;
VPSLLVQ YMM2, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 2.77
- UOPS_EXECUTED.THREAD: 6.0

Experiment 1

Instruction: VPSLLVQ YMM1, YMM2, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c4 e2 ed 47 c8       	vpsllvq ymm1,ymm2,ymm0
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 5.99
- Reference cycles: 2.77
- UOPS_EXECUTED.THREAD: 6.0

Experiment 2

Instruction: VPSLLVQ YMM1, YMM2, YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 e2 ed 47 c8       	vpsllvq ymm1,ymm2,ymm0
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 2.77
- UOPS_EXECUTED.THREAD: 6.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPSLLVQ YMM1, YMM2, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c4 e2 ed 47 c8       	vpsllvq ymm1,ymm2,ymm0
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0;
VPSLLVQ YMM2, YMM0, YMM1;
VPSLLVQ YMM0, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 5.99
- Reference cycles: 2.77
- UOPS_EXECUTED.THREAD: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPSLLVQ YMM1, YMM2, YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 e2 ed 47 c8       	vpsllvq ymm1,ymm2,ymm0
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0;
VPSLLVQ YMM2, YMM0, YMM1;
VPSLLVQ YMM0, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 2.95
- UOPS_EXECUTED.THREAD: 6.0

VPSLLVQ (YMM, YMM, YMM) - Latency

Operands

Latency operand 2 → 1: 1

Latency operand 3 → 1: 1

Latency operand 2 → 1: 1

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 1

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)