DIVPS (XMM, M128) - Latency


Operands


Latency operand 1 → 1: ≤7

Latency operand 2 → 1 (address, base register): ≤15

Latency operand 2 → 1 (address, index register): ≤15


Latency operand 1 → 1: ≤7

Experiment 1

Experiment 2

Experiment 3


Latency operand 2 → 1 (address, base register): ≤15

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Experiment 6

Experiment 7

Experiment 8

Experiment 9

Experiment 10

Experiment 11

Experiment 12

Experiment 13

Experiment 14

Experiment 15

Experiment 16

Experiment 17

Experiment 18


Latency operand 2 → 1 (address, index register): ≤15

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Experiment 6

Experiment 7

Experiment 8

Experiment 9

Experiment 10

Experiment 11

Experiment 12

Experiment 13

Experiment 14

Experiment 15

Experiment 16

Experiment 17

Experiment 18