DIV (M64) - Latency


Operands


Latency operand 1 → 2 (address, base register): 40 ≤ lat ≤ 95

Latency operand 1 → 2 (address, index register): 40 ≤ lat ≤ 95

Latency operand 1 → 3 (address, base register): 39 ≤ lat ≤ 93

Latency operand 1 → 3 (address, index register): 39 ≤ lat ≤ 93

Latency operand 2 → 2: 32 ≤ lat ≤ 87

Latency operand 2 → 3: 32 ≤ lat ≤ 87

Latency operand 3 → 2: 6 ≤ lat ≤ 74

Latency operand 3 → 3: 6 ≤ lat ≤ 73


Latency operand 1 → 2 (address, base register): 40 ≤ lat ≤ 95

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 2 (address, index register): 40 ≤ lat ≤ 95

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, base register): 39 ≤ lat ≤ 93

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, index register): 39 ≤ lat ≤ 93

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 2: 32 ≤ lat ≤ 87

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 3: 32 ≤ lat ≤ 87

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 2: 6 ≤ lat ≤ 74

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 3: 6 ≤ lat ≤ 73

Experiment 1 (fast division)

Experiment 2 (slow division)