DIV (M64) - Latency


Operands


Latency operand 1 → 2 (address, base register): 35 ≤ lat ≤ 94

Latency operand 1 → 2 (address, index register): 34 ≤ lat ≤ 94

Latency operand 1 → 3 (address, base register): 33 ≤ lat ≤ 93

Latency operand 1 → 3 (address, index register): 32 ≤ lat ≤ 93

Latency operand 2 → 2: 28 ≤ lat ≤ 89

Latency operand 2 → 3: 28 ≤ lat ≤ 90

Latency operand 3 → 2: 6 ≤ lat ≤ 78

Latency operand 3 → 3: 6 ≤ lat ≤ 78


Latency operand 1 → 2 (address, base register): 35 ≤ lat ≤ 94

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 2 (address, index register): 34 ≤ lat ≤ 94

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, base register): 33 ≤ lat ≤ 93

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, index register): 32 ≤ lat ≤ 93

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 2: 28 ≤ lat ≤ 89

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 3: 28 ≤ lat ≤ 90

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 2: 6 ≤ lat ≤ 78

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 3: 6 ≤ lat ≤ 78

Experiment 1 (fast division)

Experiment 2 (slow division)