VPCOMPRESSD_Z (ZMM, K, ZMM)

Experiment 1

Instruction: VPCOMPRESSD ZMM0 {K1}{z}, ZMM1
Chain instruction: VPMOVQ2M K1, ZMM0
Chain latency: 3

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	62 f2 fe 48 39 c8    	vpmovq2m k1,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 3.26
- UOPS_EXECUTED.THREAD: 3.0

Experiment 2

Instruction: VPCOMPRESSD ZMM0 {K1}{z}, ZMM1
Chain instruction: VPTESTNMQ K1 {K1}, ZMM0, ZMM0
Chain latency: 3

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	62 f2 fe 49 27 c8    	vptestnmq k1{k1},zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 3.05
- UOPS_EXECUTED.THREAD: 3.01

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPCOMPRESSD ZMM0 {K1}{z}, ZMM1
Chain instruction: VPMOVQ2M K1, ZMM0
Chain latency: 3

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	62 f2 fe 48 39 c8    	vpmovq2m k1,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VPCOMPRESSD ZMM1  {K1}{z}, ZMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 3.15
- UOPS_EXECUTED.THREAD: 3.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPCOMPRESSD ZMM0 {K1}{z}, ZMM1
Chain instruction: VPTESTNMQ K1 {K1}, ZMM0, ZMM0
Chain latency: 3

Code:

   0:	62 f2 7d c9 8b c8    	vpcompressd zmm0{k1}{z},zmm1
   6:	62 f2 fe 49 27 c8    	vptestnmq k1{k1},zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VPCOMPRESSD ZMM1  {K1}{z}, ZMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 2.95
- UOPS_EXECUTED.THREAD: 3.0

Experiment 1

Instruction: VPCOMPRESSD ZMM1 {K1}{z}, ZMM0
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0
Chain latency: 5

Code:

   0:	62 f2 7d c9 8b c1    	vpcompressd zmm1{k1}{z},zmm0
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 9.85
- Reference cycles: 3.2
- UOPS_EXECUTED.THREAD: 7.0

Experiment 2

Instruction: VPCOMPRESSD ZMM1 {K1}{z}, ZMM0
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0
Chain latency: 5

Code:

   0:	62 f2 7d c9 8b c1    	vpcompressd zmm1{k1}{z},zmm0
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.36
- Reference cycles: 2.79
- UOPS_EXECUTED.THREAD: 7.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPCOMPRESSD ZMM1 {K1}{z}, ZMM0
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0
Chain latency: 5

Code:

   0:	62 f2 7d c9 8b c1    	vpcompressd zmm1{k1}{z},zmm0
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VPCOMPRESSD ZMM0  {K1}{z}, ZMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 9.88
- Reference cycles: 3.41
- UOPS_EXECUTED.THREAD: 7.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPCOMPRESSD ZMM1 {K1}{z}, ZMM0
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0
Chain latency: 5

Code:

   0:	62 f2 7d c9 8b c1    	vpcompressd zmm1{k1}{z},zmm0
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VPCOMPRESSD ZMM0  {K1}{z}, ZMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.37
- Reference cycles: 2.84
- UOPS_EXECUTED.THREAD: 7.0

VPCOMPRESSD_Z (ZMM, K, ZMM) - Latency

Operands

Latency operand 2 → 1: 6

Latency operand 3 → 1: 3

Latency operand 2 → 1: 6

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 3

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)