VMOVDQA64 (YMM, K, M256)

Experiment 1

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.99
- Reference cycles: 0.31
- UOPS_EXECUTED.THREAD: 2.0

Experiment 2

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 5.99
- Reference cycles: 2.12
- UOPS_EXECUTED.THREAD: 7.0

Experiment 3

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.01
- Reference cycles: 1.91
- UOPS_EXECUTED.THREAD: 7.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VMOVDQA64 YMM0  {K1}, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.31
- UOPS_EXECUTED.THREAD: 2.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VMOVDQA64 YMM0  {K1}, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 5.98
- Reference cycles: 2.02
- UOPS_EXECUTED.THREAD: 7.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VMOVDQA64 YMM0  {K1}, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 5.99
- Reference cycles: 1.96
- UOPS_EXECUTED.THREAD: 7.0

Latency operand 2 → 1: 1

Experiment 1

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instruction: VPMOVQ2M K1, YMM0
Chain latency: 3

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	62 f2 fe 28 39 c8    	vpmovq2m k1,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.0
- Reference cycles: 1.4
- UOPS_EXECUTED.THREAD: 3.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VPMOVQ2M K1, YMM0;;VXORPS YMM0, YMM0, YMM0
Chain latency: 3

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	62 f2 fe 28 39 c8    	vpmovq2m k1,ymm0
   c:	c5 fc 57 c0          	vxorps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.0
- Reference cycles: 1.29
- UOPS_EXECUTED.THREAD: 3.0

Experiment 3

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instruction: VPTESTNMQ K1 {K1}, YMM0, YMM0
Chain latency: 3

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	62 f2 fe 29 27 c8    	vptestnmq k1{k1},ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.0
- Reference cycles: 1.4
- UOPS_EXECUTED.THREAD: 3.0

Experiment 4 (with dependency-breaking instructions)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VPTESTNMQ K1 {K1}, YMM0, YMM0;;VXORPS YMM0, YMM0, YMM0
Chain latency: 3

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	62 f2 fe 29 27 c8    	vptestnmq k1{k1},ymm0,ymm0
   c:	c5 fc 57 c0          	vxorps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.0
- Reference cycles: 1.4
- UOPS_EXECUTED.THREAD: 3.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instruction: VPMOVQ2M K1, YMM0
Chain latency: 3

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	62 f2 fe 28 39 c8    	vpmovq2m k1,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VMOVDQA64 YMM0  {K1}, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 3.99
- Reference cycles: 1.29
- UOPS_EXECUTED.THREAD: 3.0

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VPMOVQ2M K1, YMM0;;VXORPS YMM0, YMM0, YMM0
Chain latency: 3

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	62 f2 fe 28 39 c8    	vpmovq2m k1,ymm0
   c:	c5 fc 57 c0          	vxorps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VMOVDQA64 YMM0  {K1}, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.0
- Reference cycles: 1.29
- UOPS_EXECUTED.THREAD: 3.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instruction: VPTESTNMQ K1 {K1}, YMM0, YMM0
Chain latency: 3

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	62 f2 fe 29 27 c8    	vptestnmq k1{k1},ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VMOVDQA64 YMM0  {K1}, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.0
- Reference cycles: 1.34
- UOPS_EXECUTED.THREAD: 3.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VPTESTNMQ K1 {K1}, YMM0, YMM0;;VXORPS YMM0, YMM0, YMM0
Chain latency: 3

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	62 f2 fe 29 27 c8    	vptestnmq k1{k1},ymm0,ymm0
   c:	c5 fc 57 c0          	vxorps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VMOVDQA64 YMM0  {K1}, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.0
- Reference cycles: 1.29
- UOPS_EXECUTED.THREAD: 3.0

Latency operand 3 → 1 (address, base register): ≤9

Experiment 1

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥5

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 14.0
- Reference cycles: 4.6
- UOPS_EXECUTED.THREAD: 7.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;;VXORPS YMM0, YMM0, YMM0
Chain latency: ≥5

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	c5 fc 57 c0          	vxorps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 14.01
- Reference cycles: 4.75
- UOPS_EXECUTED.THREAD: 7.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥5

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VMOVDQA64 YMM0  {K1}, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 13.99
- Reference cycles: 4.81
- UOPS_EXECUTED.THREAD: 7.0

Experiment 4 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;;VXORPS YMM0, YMM0, YMM0
Chain latency: ≥5

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	c5 fc 57 c0          	vxorps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VMOVDQA64 YMM0  {K1}, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 14.01
- Reference cycles: 4.55
- UOPS_EXECUTED.THREAD: 7.0

Latency operand 3 → 1 (address, index register): ≤9

Experiment 1

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14+R13]
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥5

Code:

   0:	62 91 fd 29 6f 04 2e 	vmovdqa64 ymm0{k1},YMMWORD PTR [r14+r13*1]
   7:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   c:	4d 31 e5             	xor    r13,r12
   f:	4d 31 e5             	xor    r13,r12
  12:	4d 31 e5             	xor    r13,r12
  15:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 14.0
- Reference cycles: 4.75
- UOPS_EXECUTED.THREAD: 7.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14+R13]
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;;VXORPS YMM0, YMM0, YMM0
Chain latency: ≥5

Code:

   0:	62 91 fd 29 6f 04 2e 	vmovdqa64 ymm0{k1},YMMWORD PTR [r14+r13*1]
   7:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   c:	4d 31 e5             	xor    r13,r12
   f:	4d 31 e5             	xor    r13,r12
  12:	4d 31 e5             	xor    r13,r12
  15:	4d 31 e5             	xor    r13,r12
  18:	c5 fc 57 c0          	vxorps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 14.0
- Reference cycles: 4.65
- UOPS_EXECUTED.THREAD: 7.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14+R13]
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥5

Code:

   0:	62 91 fd 29 6f 04 2e 	vmovdqa64 ymm0{k1},YMMWORD PTR [r14+r13*1]
   7:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   c:	4d 31 e5             	xor    r13,r12
   f:	4d 31 e5             	xor    r13,r12
  12:	4d 31 e5             	xor    r13,r12
  15:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13;
VMOVDQA64 YMM0  {K1}, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 14.0
- Reference cycles: 4.6
- UOPS_EXECUTED.THREAD: 7.0

Experiment 4 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14+R13]
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;;VXORPS YMM0, YMM0, YMM0
Chain latency: ≥5

Code:

   0:	62 91 fd 29 6f 04 2e 	vmovdqa64 ymm0{k1},YMMWORD PTR [r14+r13*1]
   7:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   c:	4d 31 e5             	xor    r13,r12
   f:	4d 31 e5             	xor    r13,r12
  12:	4d 31 e5             	xor    r13,r12
  15:	4d 31 e5             	xor    r13,r12
  18:	c5 fc 57 c0          	vxorps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13;
VMOVDQA64 YMM0  {K1}, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 14.0
- Reference cycles: 4.6
- UOPS_EXECUTED.THREAD: 7.0

Latency operand 3 → 1 (memory): ≤6

Experiment 1

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM13, YMM0, YMM0, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VMOVUPD [R14], YMM13
Chain latency: ≥6

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	c5 7d c6 e8 00       	vshufpd ymm13,ymm0,ymm0,0x0
   b:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  11:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  17:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  1d:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  23:	c4 41 7d 11 2e       	vmovupd YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 12.0
- Reference cycles: 3.72
- UOPS_EXECUTED.THREAD: 9.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM13, YMM0, YMM0, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VMOVUPD [R14], YMM13;;VXORPS YMM0, YMM0, YMM0
Chain latency: ≥6

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	c5 7d c6 e8 00       	vshufpd ymm13,ymm0,ymm0,0x0
   b:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  11:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  17:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  1d:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  23:	c4 41 7d 11 2e       	vmovupd YMMWORD PTR [r14],ymm13
  28:	c5 fc 57 c0          	vxorps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.01
- Reference cycles: 3.88
- UOPS_EXECUTED.THREAD: 9.02

Experiment 3

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VPAND YMM13, YMM0, YMM0;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VMOVDQU [R14], YMM13
Chain latency: ≥6

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	c5 7d db e8          	vpand  ymm13,ymm0,ymm0
   a:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
   f:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  14:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  19:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  1e:	c4 41 7e 7f 2e       	vmovdqu YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 12.0
- Reference cycles: 4.08
- UOPS_EXECUTED.THREAD: 9.0

Experiment 4 (with dependency-breaking instructions)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VPAND YMM13, YMM0, YMM0;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VMOVDQU [R14], YMM13;;VXORPS YMM0, YMM0, YMM0
Chain latency: ≥6

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	c5 7d db e8          	vpand  ymm13,ymm0,ymm0
   a:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
   f:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  14:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  19:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  1e:	c4 41 7e 7f 2e       	vmovdqu YMMWORD PTR [r14],ymm13
  23:	c5 fc 57 c0          	vxorps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.0
- Reference cycles: 4.08
- UOPS_EXECUTED.THREAD: 9.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM13, YMM0, YMM0, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VMOVUPD [R14], YMM13
Chain latency: ≥6

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	c5 7d c6 e8 00       	vshufpd ymm13,ymm0,ymm0,0x0
   b:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  11:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  17:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  1d:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  23:	c4 41 7d 11 2e       	vmovupd YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VMOVDQA64 YMM0  {K1}, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 12.01
- Reference cycles: 3.93
- UOPS_EXECUTED.THREAD: 9.0

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM13, YMM0, YMM0, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VMOVUPD [R14], YMM13;;VXORPS YMM0, YMM0, YMM0
Chain latency: ≥6

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	c5 7d c6 e8 00       	vshufpd ymm13,ymm0,ymm0,0x0
   b:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  11:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  17:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  1d:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  23:	c4 41 7d 11 2e       	vmovupd YMMWORD PTR [r14],ymm13
  28:	c5 fc 57 c0          	vxorps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VMOVDQA64 YMM0  {K1}, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.0
- Reference cycles: 3.93
- UOPS_EXECUTED.THREAD: 9.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VPAND YMM13, YMM0, YMM0;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VMOVDQU [R14], YMM13
Chain latency: ≥6

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	c5 7d db e8          	vpand  ymm13,ymm0,ymm0
   a:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
   f:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  14:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  19:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  1e:	c4 41 7e 7f 2e       	vmovdqu YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VMOVDQA64 YMM0  {K1}, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 12.01
- Reference cycles: 3.93
- UOPS_EXECUTED.THREAD: 9.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VMOVDQA64 YMM0 {K1}, ymmword ptr [R14]
Chain instructions: VPAND YMM13, YMM0, YMM0;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VMOVDQU [R14], YMM13;;VXORPS YMM0, YMM0, YMM0
Chain latency: ≥6

Code:

   0:	62 d1 fd 29 6f 06    	vmovdqa64 ymm0{k1},YMMWORD PTR [r14]
   6:	c5 7d db e8          	vpand  ymm13,ymm0,ymm0
   a:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
   f:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  14:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  19:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  1e:	c4 41 7e 7f 2e       	vmovdqu YMMWORD PTR [r14],ymm13
  23:	c5 fc 57 c0          	vxorps ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VMOVDQA64 YMM0  {K1}, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.0
- Reference cycles: 4.03
- UOPS_EXECUTED.THREAD: 9.0

VMOVDQA64 (YMM, K, M256) - Latency

Operands

Latency operand 1 → 1: 1

Latency operand 2 → 1: 1

Latency operand 3 → 1 (address, base register): ≤9

Latency operand 3 → 1 (address, index register): ≤9

Latency operand 3 → 1 (memory): ≤6

Latency operand 1 → 1: 1

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1: 1

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Latency operand 3 → 1 (address, base register): ≤9

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Latency operand 3 → 1 (address, index register): ≤9

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Latency operand 3 → 1 (memory): ≤6

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)