VAESENC (XMM, XMM, XMM)

Experiment 1

Instruction: VAESENC XMM1, XMM0, XMM2
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	c4 e2 79 dc ca       	vaesenc xmm1,xmm0,xmm2
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.01
- Reference cycles: 3.41
- UOPS_EXECUTED.THREAD: 6.0

Experiment 2

Instruction: VAESENC XMM1, XMM0, XMM2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	c4 e2 79 dc ca       	vaesenc xmm1,xmm0,xmm2
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 3.2
- UOPS_EXECUTED.THREAD: 6.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VAESENC XMM1, XMM0, XMM2
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	c4 e2 79 dc ca       	vaesenc xmm1,xmm0,xmm2
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM2, XMM2, XMM2;
VAESENC XMM0, XMM1, XMM2;
VAESENC XMM2, XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.02
- Reference cycles: 3.41
- UOPS_EXECUTED.THREAD: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VAESENC XMM1, XMM0, XMM2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	c4 e2 79 dc ca       	vaesenc xmm1,xmm0,xmm2
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM0, XMM0, XMM0;
VXORPS XMM2, XMM2, XMM2;
VAESENC XMM0, XMM1, XMM2;
VAESENC XMM2, XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 3.31
- UOPS_EXECUTED.THREAD: 6.0

Experiment 1

Instruction: VAESENC XMM1, XMM2, XMM0
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	c4 e2 69 dc c8       	vaesenc xmm1,xmm2,xmm0
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.02
- Reference cycles: 3.2
- UOPS_EXECUTED.THREAD: 6.0

Experiment 2

Instruction: VAESENC XMM1, XMM2, XMM0
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	c4 e2 69 dc c8       	vaesenc xmm1,xmm2,xmm0
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 9.99
- Reference cycles: 3.41
- UOPS_EXECUTED.THREAD: 6.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VAESENC XMM1, XMM2, XMM0
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	c4 e2 69 dc c8       	vaesenc xmm1,xmm2,xmm0
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM0, XMM0, XMM0;
VAESENC XMM2, XMM0, XMM1;
VAESENC XMM0, XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.02
- Reference cycles: 3.26
- UOPS_EXECUTED.THREAD: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VAESENC XMM1, XMM2, XMM0
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	c4 e2 69 dc c8       	vaesenc xmm1,xmm2,xmm0
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM2, XMM2, XMM2;
VXORPS XMM0, XMM0, XMM0;
VAESENC XMM2, XMM0, XMM1;
VAESENC XMM0, XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 3.36
- UOPS_EXECUTED.THREAD: 6.0

VAESENC (XMM, XMM, XMM) - Latency

Operands

Latency operand 2 → 1: 5

Latency operand 3 → 1: 5

Latency operand 2 → 1: 5

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 5

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)