VPADDD (YMM, YMM, M256) - Latency


Operands


Latency operand 2 → 1: 1

Latency operand 3 → 1 (address, base register): ≤8

Latency operand 3 → 1 (address, index register): ≤8

Latency operand 3 → 1 (memory): ≤7


Latency operand 2 → 1: 1

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)


Latency operand 3 → 1 (address, base register): ≤8

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 3 → 1 (address, index register): ≤8

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 3 → 1 (memory): ≤7

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)