VMULPS (YMM, YMM, YMM)

Experiment 1

Instruction: VMULPS YMM1, YMM0, YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c5 fc 59 ca          	vmulps ymm1,ymm0,ymm2
   4:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   9:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  13:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  18:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 9.92
- UOPS_EXECUTED.CORE: 6.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VMULPS YMM1, YMM0, YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c5 fc 59 ca          	vmulps ymm1,ymm0,ymm2
   4:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   9:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  13:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  18:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VMOVUPD YMM2, [R14];
VMULPS YMM0, YMM1, YMM2;
VMULPS YMM2, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 9.92
- UOPS_EXECUTED.CORE: 6.0

Experiment 1

Instruction: VMULPS YMM1, YMM2, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c5 ec 59 c8          	vmulps ymm1,ymm2,ymm0
   4:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   9:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  13:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  18:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 9.92
- UOPS_EXECUTED.CORE: 6.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VMULPS YMM1, YMM2, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c5 ec 59 c8          	vmulps ymm1,ymm2,ymm0
   4:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   9:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  13:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  18:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VMOVUPD YMM0, [R14];
VMULPS YMM2, YMM0, YMM1;
VMULPS YMM0, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 9.92
- UOPS_EXECUTED.CORE: 6.0

VMULPS (YMM, YMM, YMM) - Latency

Operands

Latency operand 2 → 1: 5

Latency operand 3 → 1: 5

Latency operand 2 → 1: 5

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 5

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)