VMOVDQA (M256, YMM)

Experiment 1

Instruction: VMOVDQA ymmword ptr [R14], YMM0
Chain instructions: MOV R12, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12
Chain latency: ≥7

Code:

   0:	c4 c1 7d 7f 06       	vmovdqa YMMWORD PTR [r14],ymm0
   5:	4d 8b 26             	mov    r12,QWORD PTR [r14]
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 16.67
- Reference cycles: 16.69
- UOPS_EXECUTED.CORE: 9.0

Experiment 2 (with additional nop)

Instruction: VMOVDQA ymmword ptr [R14], YMM0
Chain instructions: MOV R12, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12;nop
Chain latency: ≥7

Code:

   0:	c4 c1 7d 7f 06       	vmovdqa YMMWORD PTR [r14],ymm0
   5:	4d 8b 26             	mov    r12,QWORD PTR [r14]
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 16.24
- Reference cycles: 16.16
- UOPS_EXECUTED.CORE: 9.0

Latency operand 1 → 1 (address, index register): ≤9

Experiment 1

Instruction: VMOVDQA ymmword ptr [R14+R13], YMM0
Chain instructions: MOV R12, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12
Chain latency: ≥7

Code:

   0:	c4 81 7d 7f 04 2e    	vmovdqa YMMWORD PTR [r14+r13*1],ymm0
   6:	4f 8b 24 2e          	mov    r12,QWORD PTR [r14+r13*1]
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 31 e5             	xor    r13,r12
  19:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 16.9
- Reference cycles: 16.91
- UOPS_EXECUTED.CORE: 9.0

Experiment 2 (with additional nop)

Instruction: VMOVDQA ymmword ptr [R14+R13], YMM0
Chain instructions: MOV R12, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12;nop
Chain latency: ≥7

Code:

   0:	c4 81 7d 7f 04 2e    	vmovdqa YMMWORD PTR [r14+r13*1],ymm0
   6:	4f 8b 24 2e          	mov    r12,QWORD PTR [r14+r13*1]
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 31 e5             	xor    r13,r12
  19:	4d 31 e5             	xor    r13,r12
  1c:	90                   	nop

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 16.05
- Reference cycles: 16.16
- UOPS_EXECUTED.CORE: 9.0

Latency operand 2 → 1: ≤5

Experiment 1

Instruction: VMOVDQA ymmword ptr [R14], YMM0
Chain instructions: VMOVUPD XMM13, [R14];VSHUFPD XMM0, XMM13, XMM13, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: ≥6

Code:

   0:	c4 c1 7d 7f 06       	vmovdqa YMMWORD PTR [r14],ymm0
   5:	c4 41 79 10 2e       	vmovupd xmm13,XMMWORD PTR [r14]
   a:	c4 c1 11 c6 c5 00    	vshufpd xmm0,xmm13,xmm13,0x0
  10:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  15:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 11.0
- Reference cycles: 10.99
- UOPS_EXECUTED.CORE: 8.0

VMOVDQA (M256, YMM) - Latency

Operands

Latency operand 1 → 1 (address, base register): ≤9

Latency operand 1 → 1 (address, index register): ≤9

Latency operand 2 → 1: ≤5

Latency operand 1 → 1 (address, base register): ≤9

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (address, index register): ≤9

Experiment 1

Experiment 2 (with additional nop)

Latency operand 2 → 1: ≤5

Experiment 1