VADDSUBPS (YMM, YMM, M256)

Experiment 1

Instruction: VADDSUBPS YMM1, YMM0, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c4 c1 7f d0 0e       	vaddsubps ymm1,ymm0,YMMWORD PTR [r14]
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.0
- Reference cycles: 8.0
- UOPS_EXECUTED.CORE: 7.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VADDSUBPS YMM1, YMM0, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c4 c1 7f d0 0e       	vaddsubps ymm1,ymm0,YMMWORD PTR [r14]
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VADDSUBPS YMM0, YMM1, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.0
- Reference cycles: 8.0
- UOPS_EXECUTED.CORE: 7.0

Latency operand 3 → 1 (address, base register): ≤10

Experiment 1

Instruction: VADDSUBPS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥5

Code:

   0:	c4 c1 77 d0 06       	vaddsubps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   a:	4d 31 e6             	xor    r14,r12
   d:	4d 31 e6             	xor    r14,r12
  10:	4d 31 e6             	xor    r14,r12
  13:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 15.0
- Reference cycles: 14.83
- UOPS_EXECUTED.CORE: 7.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VADDSUBPS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥5

Code:

   0:	c4 c1 77 d0 06       	vaddsubps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   a:	4d 31 e6             	xor    r14,r12
   d:	4d 31 e6             	xor    r14,r12
  10:	4d 31 e6             	xor    r14,r12
  13:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VADDSUBPS YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 15.0
- Reference cycles: 15.09
- UOPS_EXECUTED.CORE: 7.0

Latency operand 3 → 1 (address, index register): ≤10

Experiment 1

Instruction: VADDSUBPS YMM0, YMM1, ymmword ptr [R14+R13]
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥5

Code:

   0:	c4 81 77 d0 04 2e    	vaddsubps ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e5             	xor    r13,r12
   e:	4d 31 e5             	xor    r13,r12
  11:	4d 31 e5             	xor    r13,r12
  14:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 15.0
- Reference cycles: 15.04
- UOPS_EXECUTED.CORE: 7.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VADDSUBPS YMM0, YMM1, ymmword ptr [R14+R13]
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥5

Code:

   0:	c4 81 77 d0 04 2e    	vaddsubps ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e5             	xor    r13,r12
   e:	4d 31 e5             	xor    r13,r12
  11:	4d 31 e5             	xor    r13,r12
  14:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
XOR R13, R13;
VADDSUBPS YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 15.0
- Reference cycles: 14.93
- UOPS_EXECUTED.CORE: 7.0

Latency operand 3 → 1 (memory): ≤9

Experiment 1

Instruction: VADDSUBPS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM13, YMM0, YMM0, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VMOVUPD [R14], YMM13
Chain latency: ≥6

Code:

   0:	c4 c1 77 d0 06       	vaddsubps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 7d c6 e8 00       	vshufpd ymm13,ymm0,ymm0,0x0
   a:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  10:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  16:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  1c:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  22:	c4 41 7d 11 2e       	vmovupd YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 15.0
- Reference cycles: 15.25
- UOPS_EXECUTED.CORE: 9.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VADDSUBPS YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM13, YMM0, YMM0, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VMOVUPD [R14], YMM13
Chain latency: ≥6

Code:

   0:	c4 c1 77 d0 06       	vaddsubps ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 7d c6 e8 00       	vshufpd ymm13,ymm0,ymm0,0x0
   a:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  10:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  16:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  1c:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  22:	c4 41 7d 11 2e       	vmovupd YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VADDSUBPS YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 15.0
- Reference cycles: 14.93
- UOPS_EXECUTED.CORE: 9.0

VADDSUBPS (YMM, YMM, M256) - Latency

Operands

Latency operand 2 → 1: 3

Latency operand 3 → 1 (address, base register): ≤10

Latency operand 3 → 1 (address, index register): ≤10

Latency operand 3 → 1 (memory): ≤9

Latency operand 2 → 1: 3

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (address, base register): ≤10

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (address, index register): ≤10

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (memory): ≤9

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)