DIV (M64) - Latency


Operands


Latency operand 1 → 2 (address, base register): 34 ≤ lat ≤ 98

Latency operand 1 → 2 (address, index register): 34 ≤ lat ≤ 98

Latency operand 1 → 3 (address, base register): 33 ≤ lat ≤ 97

Latency operand 1 → 3 (address, index register): 33 ≤ lat ≤ 97

Latency operand 2 → 2: 30 ≤ lat ≤ 94

Latency operand 2 → 3: 31 ≤ lat ≤ 95

Latency operand 3 → 2: 5 ≤ lat ≤ 83

Latency operand 3 → 3: 5 ≤ lat ≤ 82


Latency operand 1 → 2 (address, base register): 34 ≤ lat ≤ 98

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 2 (address, index register): 34 ≤ lat ≤ 98

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, base register): 33 ≤ lat ≤ 97

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, index register): 33 ≤ lat ≤ 97

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 2: 30 ≤ lat ≤ 94

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 3: 31 ≤ lat ≤ 95

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 2: 5 ≤ lat ≤ 83

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 3: 5 ≤ lat ≤ 82

Experiment 1 (fast division)

Experiment 2 (slow division)