ADD (M8, I8)

Experiment 1

Instruction: ADD byte ptr [R14], 2
Chain instructions: MOV R12B, [R14];MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;XOR R14, R12; XOR R14, R12
Chain latency: ≥13

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	45 8a 26             	mov    r12b,BYTE PTR [r14]
   7:	4d 0f be e4          	movsx  r12,r12b
   b:	4d 0f be e4          	movsx  r12,r12b
   f:	4d 0f be e4          	movsx  r12,r12b
  13:	4d 0f be e4          	movsx  r12,r12b
  17:	4d 0f be e4          	movsx  r12,r12b
  1b:	4d 0f be e4          	movsx  r12,r12b
  1f:	4d 0f be e4          	movsx  r12,r12b
  23:	4d 0f be e4          	movsx  r12,r12b
  27:	4d 0f be e4          	movsx  r12,r12b
  2b:	4d 0f be e4          	movsx  r12,r12b
  2f:	4d 31 e6             	xor    r14,r12
  32:	4d 31 e6             	xor    r14,r12

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 23.84
- Reference cycles: 21.17
- UOPS_EXECUTED.CORE: 18.0

Experiment 2 (with additional nop)

Instruction: ADD byte ptr [R14], 2
Chain instructions: MOV R12B, [R14];MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;XOR R14, R12; XOR R14, R12;nop
Chain latency: ≥13

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	45 8a 26             	mov    r12b,BYTE PTR [r14]
   7:	4d 0f be e4          	movsx  r12,r12b
   b:	4d 0f be e4          	movsx  r12,r12b
   f:	4d 0f be e4          	movsx  r12,r12b
  13:	4d 0f be e4          	movsx  r12,r12b
  17:	4d 0f be e4          	movsx  r12,r12b
  1b:	4d 0f be e4          	movsx  r12,r12b
  1f:	4d 0f be e4          	movsx  r12,r12b
  23:	4d 0f be e4          	movsx  r12,r12b
  27:	4d 0f be e4          	movsx  r12,r12b
  2b:	4d 0f be e4          	movsx  r12,r12b
  2f:	4d 31 e6             	xor    r14,r12
  32:	4d 31 e6             	xor    r14,r12
  35:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 23.04
- Reference cycles: 20.48
- UOPS_EXECUTED.CORE: 18.0

Latency operand 1 → 1 (address, index register): ≤11

Experiment 1

Instruction: ADD byte ptr [R14+R13], 2
Chain instructions: MOV R12B, [R14+R13];MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;XOR R13, R12; XOR R13, R12
Chain latency: ≥13

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	47 8a 24 2e          	mov    r12b,BYTE PTR [r14+r13*1]
   9:	4d 0f be e4          	movsx  r12,r12b
   d:	4d 0f be e4          	movsx  r12,r12b
  11:	4d 0f be e4          	movsx  r12,r12b
  15:	4d 0f be e4          	movsx  r12,r12b
  19:	4d 0f be e4          	movsx  r12,r12b
  1d:	4d 0f be e4          	movsx  r12,r12b
  21:	4d 0f be e4          	movsx  r12,r12b
  25:	4d 0f be e4          	movsx  r12,r12b
  29:	4d 0f be e4          	movsx  r12,r12b
  2d:	4d 0f be e4          	movsx  r12,r12b
  31:	4d 31 e5             	xor    r13,r12
  34:	4d 31 e5             	xor    r13,r12

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 24.77
- Reference cycles: 22.08
- UOPS_EXECUTED.CORE: 18.0

Experiment 2 (with additional nop)

Instruction: ADD byte ptr [R14+R13], 2
Chain instructions: MOV R12B, [R14+R13];MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;MOVSX R12, R12B;XOR R13, R12; XOR R13, R12;nop
Chain latency: ≥13

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	47 8a 24 2e          	mov    r12b,BYTE PTR [r14+r13*1]
   9:	4d 0f be e4          	movsx  r12,r12b
   d:	4d 0f be e4          	movsx  r12,r12b
  11:	4d 0f be e4          	movsx  r12,r12b
  15:	4d 0f be e4          	movsx  r12,r12b
  19:	4d 0f be e4          	movsx  r12,r12b
  1d:	4d 0f be e4          	movsx  r12,r12b
  21:	4d 0f be e4          	movsx  r12,r12b
  25:	4d 0f be e4          	movsx  r12,r12b
  29:	4d 0f be e4          	movsx  r12,r12b
  2d:	4d 0f be e4          	movsx  r12,r12b
  31:	4d 31 e5             	xor    r13,r12
  34:	4d 31 e5             	xor    r13,r12
  37:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 15.0
- Core cycles: 23.9
- Reference cycles: 21.28
- UOPS_EXECUTED.CORE: 18.0

Latency operand 1 → 1 (memory): 6

Latency operand 1 → 3 (address, base register): 6

Experiment 1

Instruction: ADD byte ptr [R14], 2
Chain instruction: CMOVS R14, R14
Chain latency: 2

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	4d 0f 48 f6          	cmovs  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 8.0
- Reference cycles: 7.09
- UOPS_EXECUTED.CORE: 6.0

Experiment 2 (with dependency-breaking instructions)

Instruction: ADD byte ptr [R14], 2
Chain instructions: CMOVS R14, R14;MOV byte ptr [R14], 0
Chain latency: 2

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	4d 0f 48 f6          	cmovs  r14,r14
   8:	41 c6 06 00          	mov    BYTE PTR [r14],0x0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 13.14
- Reference cycles: 11.63
- UOPS_EXECUTED.CORE: 8.0

Experiment 3

Instruction: ADD byte ptr [R14], 2
Chain instruction: CMOVC R14, R14
Chain latency: 2

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	4d 0f 42 f6          	cmovb  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 8.0
- Reference cycles: 7.15
- UOPS_EXECUTED.CORE: 6.0

Experiment 4 (with dependency-breaking instructions)

Instruction: ADD byte ptr [R14], 2
Chain instructions: CMOVC R14, R14;MOV byte ptr [R14], 0
Chain latency: 2

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	4d 0f 42 f6          	cmovb  r14,r14
   8:	41 c6 06 00          	mov    BYTE PTR [r14],0x0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 13.2
- Reference cycles: 11.63
- UOPS_EXECUTED.CORE: 8.0

Experiment 5

Instruction: ADD byte ptr [R14], 2
Chain instruction: CMOVP R14, R14
Chain latency: 2

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	4d 0f 4a f6          	cmovp  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 8.0
- Reference cycles: 7.09
- UOPS_EXECUTED.CORE: 6.0

Experiment 6 (with dependency-breaking instructions)

Instruction: ADD byte ptr [R14], 2
Chain instructions: CMOVP R14, R14;MOV byte ptr [R14], 0
Chain latency: 2

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	4d 0f 4a f6          	cmovp  r14,r14
   8:	41 c6 06 00          	mov    BYTE PTR [r14],0x0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 13.2
- Reference cycles: 11.79
- UOPS_EXECUTED.CORE: 8.0

Experiment 7

Instruction: ADD byte ptr [R14], 2
Chain instruction: CMOVZ R14, R14
Chain latency: 2

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	4d 0f 44 f6          	cmove  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 8.0
- Reference cycles: 7.15
- UOPS_EXECUTED.CORE: 6.0

Experiment 8 (with dependency-breaking instructions)

Instruction: ADD byte ptr [R14], 2
Chain instructions: CMOVZ R14, R14;MOV byte ptr [R14], 0
Chain latency: 2

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	4d 0f 44 f6          	cmove  r14,r14
   8:	41 c6 06 00          	mov    BYTE PTR [r14],0x0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 13.2
- Reference cycles: 11.68
- UOPS_EXECUTED.CORE: 8.0

Experiment 9

Instruction: ADD byte ptr [R14], 2
Chain instruction: CMOVO R14, R14
Chain latency: 2

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	4d 0f 40 f6          	cmovo  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 8.0
- Reference cycles: 7.15
- UOPS_EXECUTED.CORE: 6.0

Experiment 10 (with dependency-breaking instructions)

Instruction: ADD byte ptr [R14], 2
Chain instructions: CMOVO R14, R14;MOV byte ptr [R14], 0
Chain latency: 2

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	4d 0f 40 f6          	cmovo  r14,r14
   8:	41 c6 06 00          	mov    BYTE PTR [r14],0x0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 13.2
- Reference cycles: 11.63
- UOPS_EXECUTED.CORE: 8.0

Latency operand 1 → 3 (address, index register): 6

Experiment 1

Instruction: ADD byte ptr [R14+R13], 2
Chain instruction: CMOVS R13, R13
Chain latency: 2

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	4d 0f 48 ed          	cmovs  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 8.03
- Reference cycles: 7.15
- UOPS_EXECUTED.CORE: 6.0

Experiment 2 (with dependency-breaking instructions)

Instruction: ADD byte ptr [R14+R13], 2
Chain instructions: CMOVS R13, R13;MOV byte ptr [R14], 0
Chain latency: 2

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	4d 0f 48 ed          	cmovs  r13,r13
   9:	41 c6 06 00          	mov    BYTE PTR [r14],0x0

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 8.08
- Reference cycles: 7.04
- UOPS_EXECUTED.CORE: 8.0

Experiment 3

Instruction: ADD byte ptr [R14+R13], 2
Chain instruction: CMOVC R13, R13
Chain latency: 2

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	4d 0f 42 ed          	cmovb  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 8.07
- Reference cycles: 7.09
- UOPS_EXECUTED.CORE: 6.0

Experiment 4 (with dependency-breaking instructions)

Instruction: ADD byte ptr [R14+R13], 2
Chain instructions: CMOVC R13, R13;MOV byte ptr [R14], 0
Chain latency: 2

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	4d 0f 42 ed          	cmovb  r13,r13
   9:	41 c6 06 00          	mov    BYTE PTR [r14],0x0

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 8.14
- Reference cycles: 7.36
- UOPS_EXECUTED.CORE: 8.0

Experiment 5

Instruction: ADD byte ptr [R14+R13], 2
Chain instruction: CMOVP R13, R13
Chain latency: 2

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	4d 0f 4a ed          	cmovp  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 8.07
- Reference cycles: 7.09
- UOPS_EXECUTED.CORE: 6.0

Experiment 6 (with dependency-breaking instructions)

Instruction: ADD byte ptr [R14+R13], 2
Chain instructions: CMOVP R13, R13;MOV byte ptr [R14], 0
Chain latency: 2

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	4d 0f 4a ed          	cmovp  r13,r13
   9:	41 c6 06 00          	mov    BYTE PTR [r14],0x0

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 8.04
- Reference cycles: 7.09
- UOPS_EXECUTED.CORE: 8.0

Experiment 7

Instruction: ADD byte ptr [R14+R13], 2
Chain instruction: CMOVZ R13, R13
Chain latency: 2

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	4d 0f 44 ed          	cmove  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 8.07
- Reference cycles: 7.09
- UOPS_EXECUTED.CORE: 6.0

Experiment 8 (with dependency-breaking instructions)

Instruction: ADD byte ptr [R14+R13], 2
Chain instructions: CMOVZ R13, R13;MOV byte ptr [R14], 0
Chain latency: 2

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	4d 0f 44 ed          	cmove  r13,r13
   9:	41 c6 06 00          	mov    BYTE PTR [r14],0x0

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 8.14
- Reference cycles: 7.31
- UOPS_EXECUTED.CORE: 8.0

Experiment 9

Instruction: ADD byte ptr [R14+R13], 2
Chain instruction: CMOVO R13, R13
Chain latency: 2

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	4d 0f 40 ed          	cmovo  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 8.07
- Reference cycles: 7.09
- UOPS_EXECUTED.CORE: 6.0

Experiment 10 (with dependency-breaking instructions)

Instruction: ADD byte ptr [R14+R13], 2
Chain instructions: CMOVO R13, R13;MOV byte ptr [R14], 0
Chain latency: 2

Code:

   0:	43 80 04 2e 02       	add    BYTE PTR [r14+r13*1],0x2
   5:	4d 0f 40 ed          	cmovo  r13,r13
   9:	41 c6 06 00          	mov    BYTE PTR [r14],0x0

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 8.06
- Reference cycles: 7.15
- UOPS_EXECUTED.CORE: 8.0

Latency operand 1 → 3 (memory): ≤5

Experiment 1

Instruction: ADD byte ptr [R14], 2
Chain instructions: CMOVS R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12B
Chain latency: ≥13

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	4d 0f 48 e4          	cmovs  r12,r12
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 63 e4             	movsxd r12,r12d
  20:	4d 63 e4             	movsxd r12,r12d
  23:	4d 63 e4             	movsxd r12,r12d
  26:	45 88 26             	mov    BYTE PTR [r14],r12b

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 18.0
- Reference cycles: 16.0
- UOPS_EXECUTED.CORE: 18.0

Experiment 2

Instruction: ADD byte ptr [R14], 2
Chain instructions: CMOVC R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12B
Chain latency: ≥13

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	4d 0f 42 e4          	cmovb  r12,r12
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 63 e4             	movsxd r12,r12d
  20:	4d 63 e4             	movsxd r12,r12d
  23:	4d 63 e4             	movsxd r12,r12d
  26:	45 88 26             	mov    BYTE PTR [r14],r12b

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 18.0
- Reference cycles: 16.05
- UOPS_EXECUTED.CORE: 18.0

Experiment 3

Instruction: ADD byte ptr [R14], 2
Chain instructions: CMOVP R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12B
Chain latency: ≥13

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	4d 0f 4a e4          	cmovp  r12,r12
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 63 e4             	movsxd r12,r12d
  20:	4d 63 e4             	movsxd r12,r12d
  23:	4d 63 e4             	movsxd r12,r12d
  26:	45 88 26             	mov    BYTE PTR [r14],r12b

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 18.0
- Reference cycles: 16.0
- UOPS_EXECUTED.CORE: 18.0

Experiment 4

Instruction: ADD byte ptr [R14], 2
Chain instructions: CMOVZ R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12B
Chain latency: ≥13

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	4d 0f 44 e4          	cmove  r12,r12
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 63 e4             	movsxd r12,r12d
  20:	4d 63 e4             	movsxd r12,r12d
  23:	4d 63 e4             	movsxd r12,r12d
  26:	45 88 26             	mov    BYTE PTR [r14],r12b

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 18.0
- Reference cycles: 16.0
- UOPS_EXECUTED.CORE: 18.0

Experiment 5

Instruction: ADD byte ptr [R14], 2
Chain instructions: CMOVO R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12B
Chain latency: ≥13

Code:

   0:	41 80 06 02          	add    BYTE PTR [r14],0x2
   4:	4d 0f 40 e4          	cmovo  r12,r12
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 63 e4             	movsxd r12,r12d
  20:	4d 63 e4             	movsxd r12,r12d
  23:	4d 63 e4             	movsxd r12,r12d
  26:	45 88 26             	mov    BYTE PTR [r14],r12b

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 18.0
- Reference cycles: 16.0
- UOPS_EXECUTED.CORE: 18.0

ADD (M8, I8) - Latency

Operands

Latency operand 1 → 1 (address, base register): ≤10

Latency operand 1 → 1 (address, index register): ≤11

Latency operand 1 → 1 (memory): 6

Latency operand 1 → 3 (address, base register): 6

Latency operand 1 → 3 (address, index register): 6

Latency operand 1 → 3 (memory): ≤5

Latency operand 1 → 1 (address, base register): ≤10

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (address, index register): ≤11

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (memory): 6

Experiment 1

Experiment 2

Latency operand 1 → 3 (address, base register): 6

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5

Experiment 6 (with dependency-breaking instructions)

Experiment 7

Experiment 8 (with dependency-breaking instructions)

Experiment 9

Experiment 10 (with dependency-breaking instructions)

Latency operand 1 → 3 (address, index register): 6

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5

Experiment 6 (with dependency-breaking instructions)

Experiment 7

Experiment 8 (with dependency-breaking instructions)

Experiment 9

Experiment 10 (with dependency-breaking instructions)

Latency operand 1 → 3 (memory): ≤5

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5