ADD (M8, I8) - Latency (IACA 2.1)

Latency Analysis Report
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Latency: 7 Cycles

The Resource delay is counted since all the sources of the instructions are ready
and until the needed resource becomes available

| Inst |                 Resource Delay In Cycles                  |    |
| Num  | 0  - DV | 1  | 2  - D  | 3  - D  | 4  | 5  | 6  | 7  | FE |    |
-------------------------------------------------------------------------
|  0   |         |    |         |         |    |    |    |    |    | CP | add byte ptr [r14], 0x2

Resource Conflict on Critical Paths: 
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|  Port  | 0  - DV | 1  | 2  - D  | 3  - D  | 4  | 5  | 6  | 7  |
-----------------------------------------------------------------
| Cycles | 0    0  | 0  | 0    0  | 0    0  | 0  | 0  | 0  | 0  |
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List Of Delays On Critical Paths
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