POR (XMM, XMM)

Experiment 1

Instruction: POR XMM0, XMM1

Code:

   0:	66 0f eb c1          	por    xmm0,xmm1

Init:
```
PXOR XMM0, XMM0;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.69
- UOPS_RETIRED.ANY: 1.0

Experiment 2

Instruction: POR XMM0, XMM1
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	66 0f eb c1          	por    xmm0,xmm1
   4:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   9:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  13:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  18:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:
```
PXOR XMM0, XMM0;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.68
- UOPS_RETIRED.ANY: 6.0

Experiment 3

Instruction: POR XMM0, XMM1
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	66 0f eb c1          	por    xmm0,xmm1
   4:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   9:	66 0f db c0          	pand   xmm0,xmm0
   d:	66 0f db c0          	pand   xmm0,xmm0
  11:	66 0f db c0          	pand   xmm0,xmm0
  15:	66 0f db c0          	pand   xmm0,xmm0

Init:
```
PXOR XMM0, XMM0;
PXOR XMM1, XMM1
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.68
- UOPS_RETIRED.ANY: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: POR XMM0, XMM1

Code:

   0:	66 0f eb c1          	por    xmm0,xmm1

Init:

PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
POR XMM0, XMM1;
POR XMM1, XMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.35
- UOPS_RETIRED.ANY: 1.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: POR XMM0, XMM1
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	66 0f eb c1          	por    xmm0,xmm1
   4:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   9:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  13:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  18:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
POR XMM0, XMM1;
POR XMM1, XMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.85
- UOPS_RETIRED.ANY: 6.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: POR XMM0, XMM1
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	66 0f eb c1          	por    xmm0,xmm1
   4:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   9:	66 0f db c0          	pand   xmm0,xmm0
   d:	66 0f db c0          	pand   xmm0,xmm0
  11:	66 0f db c0          	pand   xmm0,xmm0
  15:	66 0f db c0          	pand   xmm0,xmm0

Init:

PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
POR XMM0, XMM1;
POR XMM1, XMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.85
- UOPS_RETIRED.ANY: 6.0

Experiment 1

Instruction: POR XMM1, XMM0
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	66 0f eb c8          	por    xmm1,xmm0
   4:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   9:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  13:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  18:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:
```
PXOR XMM1, XMM1;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.68
- UOPS_RETIRED.ANY: 6.0

Experiment 2

Instruction: POR XMM1, XMM0
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	66 0f eb c8          	por    xmm1,xmm0
   4:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   9:	66 0f db c0          	pand   xmm0,xmm0
   d:	66 0f db c0          	pand   xmm0,xmm0
  11:	66 0f db c0          	pand   xmm0,xmm0
  15:	66 0f db c0          	pand   xmm0,xmm0

Init:
```
PXOR XMM1, XMM1;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 5.03
- UOPS_RETIRED.ANY: 6.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: POR XMM1, XMM0
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	66 0f eb c8          	por    xmm1,xmm0
   4:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   9:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  13:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  18:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

PXOR XMM1, XMM1;
PXOR XMM0, XMM0;
POR XMM1, XMM0;
POR XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 5.2
- UOPS_RETIRED.ANY: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: POR XMM1, XMM0
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	66 0f eb c8          	por    xmm1,xmm0
   4:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   9:	66 0f db c0          	pand   xmm0,xmm0
   d:	66 0f db c0          	pand   xmm0,xmm0
  11:	66 0f db c0          	pand   xmm0,xmm0
  15:	66 0f db c0          	pand   xmm0,xmm0

Init:

PXOR XMM1, XMM1;
PXOR XMM0, XMM0;
POR XMM1, XMM0;
POR XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.85
- UOPS_RETIRED.ANY: 6.0

POR (XMM, XMM) - Latency

Operands

Latency operand 1 → 1: 1

Latency operand 2 → 1: 1

Latency operand 1 → 1: 1

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1: 1

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)