MOVUPS (M128, XMM)

Experiment 1

Instruction: MOVUPS xmmword ptr [R14], XMM0
Chain instructions: MOV R12, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12
Chain latency: ≥9

Code:

   0:	41 0f 11 06          	movups XMMWORD PTR [r14],xmm0
   4:	4d 8b 26             	mov    r12,QWORD PTR [r14]
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 31 e6             	xor    r14,r12
  1c:	4d 31 e6             	xor    r14,r12

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 18.53
- Reference cycles: 18.53
- RS_UOPS_DISPATCHED: 18.0

Experiment 2 (with additional nop)

Instruction: MOVUPS xmmword ptr [R14], XMM0
Chain instructions: MOV R12, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12;nop
Chain latency: ≥9

Code:

   0:	41 0f 11 06          	movups XMMWORD PTR [r14],xmm0
   4:	4d 8b 26             	mov    r12,QWORD PTR [r14]
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 31 e6             	xor    r14,r12
  1c:	4d 31 e6             	xor    r14,r12
  1f:	90                   	nop

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 18.75
- Reference cycles: 18.76
- RS_UOPS_DISPATCHED: 19.0

Latency operand 1 → 1 (address, index register): ≤9

Experiment 1

Instruction: MOVUPS xmmword ptr [R14+R13], XMM0
Chain instructions: MOV R12, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12
Chain latency: ≥9

Code:

   0:	43 0f 11 04 2e       	movups XMMWORD PTR [r14+r13*1],xmm0
   5:	4f 8b 24 2e          	mov    r12,QWORD PTR [r14+r13*1]
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 31 e5             	xor    r13,r12
  1e:	4d 31 e5             	xor    r13,r12

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 18.53
- Reference cycles: 18.53
- RS_UOPS_DISPATCHED: 18.0

Experiment 2 (with additional nop)

Instruction: MOVUPS xmmword ptr [R14+R13], XMM0
Chain instructions: MOV R12, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12;nop
Chain latency: ≥9

Code:

   0:	43 0f 11 04 2e       	movups XMMWORD PTR [r14+r13*1],xmm0
   5:	4f 8b 24 2e          	mov    r12,QWORD PTR [r14+r13*1]
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 31 e5             	xor    r13,r12
  1e:	4d 31 e5             	xor    r13,r12
  21:	90                   	nop

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 18.74
- Reference cycles: 18.76
- RS_UOPS_DISPATCHED: 19.0

Latency operand 2 → 1: ≤7

Experiment 1

Instruction: MOVUPS xmmword ptr [R14], XMM0
Chain instructions: MOVUPD XMM13, [R14];SHUFPD XMM0, XMM13, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: ≥8

Code:

   0:	41 0f 11 06          	movups XMMWORD PTR [r14],xmm0
   4:	66 45 0f 10 2e       	movupd xmm13,XMMWORD PTR [r14]
   9:	66 41 0f c6 c5 00    	shufpd xmm0,xmm13,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  28:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 16.03
- Reference cycles: 16.01
- RS_UOPS_DISPATCHED: 20.0

Experiment 2

Instruction: MOVUPS xmmword ptr [R14], XMM0
Chain instructions: MOVDQU XMM13, [R14];PSHUFD XMM0, XMM13, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: ≥11

Code:

   0:	41 0f 11 06          	movups XMMWORD PTR [r14],xmm0
   4:	f3 45 0f 6f 2e       	movdqu xmm13,XMMWORD PTR [r14]
   9:	66 41 0f 70 c5 00    	pshufd xmm0,xmm13,0x0
   f:	66 0f db c0          	pand   xmm0,xmm0
  13:	66 0f db c0          	pand   xmm0,xmm0
  17:	66 0f db c0          	pand   xmm0,xmm0
  1b:	66 0f db c0          	pand   xmm0,xmm0
  1f:	66 0f db c0          	pand   xmm0,xmm0
  23:	66 0f db c0          	pand   xmm0,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 18.16
- Reference cycles: 18.16
- RS_UOPS_DISPATCHED: 21.0

MOVUPS (M128, XMM) - Latency

Operands

Latency operand 1 → 1 (address, base register): ≤9

Latency operand 1 → 1 (address, index register): ≤9

Latency operand 2 → 1: ≤7

Latency operand 1 → 1 (address, base register): ≤9

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (address, index register): ≤9

Experiment 1

Experiment 2 (with additional nop)

Latency operand 2 → 1: ≤7

Experiment 1

Experiment 2