VPADDQ (ZMM, K, ZMM, ZMM)

Experiment 1

Instruction: VPADDQ ZMM0 {K1}, ZMM1, ZMM2

Code:

   0:	62 f1 f5 49 d4 c2    	vpaddq zmm0{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.77
- UOPS_EXECUTED.THREAD: 1.0

Experiment 2

Instruction: VPADDQ ZMM0 {K1}, ZMM1, ZMM2
Chain instructions: VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0
Chain latency: 5

Code:

   0:	62 f1 f5 49 d4 c2    	vpaddq zmm0{k1},zmm1,zmm2
   6:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.29
- UOPS_EXECUTED.THREAD: 6.0

Experiment 3

Instruction: VPADDQ ZMM0 {K1}, ZMM1, ZMM2
Chain instructions: VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0
Chain latency: 5

Code:

   0:	62 f1 f5 49 d4 c2    	vpaddq zmm0{k1},zmm1,zmm2
   6:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.45
- UOPS_EXECUTED.THREAD: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPADDQ ZMM0 {K1}, ZMM1, ZMM2

Code:

   0:	62 f1 f5 49 d4 c2    	vpaddq zmm0{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VPADDQ ZMM0  {K1}, ZMM1, ZMM2;
VPADDQ ZMM1  {K1}, ZMM0, ZMM2;
VPADDQ ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.46
- UOPS_EXECUTED.THREAD: 1.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VPADDQ ZMM0 {K1}, ZMM1, ZMM2
Chain instructions: VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0
Chain latency: 5

Code:

   0:	62 f1 f5 49 d4 c2    	vpaddq zmm0{k1},zmm1,zmm2
   6:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VPADDQ ZMM0  {K1}, ZMM1, ZMM2;
VPADDQ ZMM1  {K1}, ZMM0, ZMM2;
VPADDQ ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.29
- UOPS_EXECUTED.THREAD: 6.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: VPADDQ ZMM0 {K1}, ZMM1, ZMM2
Chain instructions: VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0
Chain latency: 5

Code:

   0:	62 f1 f5 49 d4 c2    	vpaddq zmm0{k1},zmm1,zmm2
   6:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VPADDQ ZMM0  {K1}, ZMM1, ZMM2;
VPADDQ ZMM1  {K1}, ZMM0, ZMM2;
VPADDQ ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.45
- UOPS_EXECUTED.THREAD: 6.0

Latency operand 2 → 1: 1

Experiment 1

Instruction: VPADDQ ZMM0 {K1}, ZMM1, ZMM2
Chain instruction: VPMOVQ2M K1, ZMM0
Chain latency: 3

Code:

   0:	62 f1 f5 49 d4 c2    	vpaddq zmm0{k1},zmm1,zmm2
   6:	62 f2 fe 48 39 c8    	vpmovq2m k1,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.0
- Reference cycles: 2.45
- UOPS_EXECUTED.THREAD: 2.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VPADDQ ZMM0 {K1}, ZMM1, ZMM2
Chain instructions: VPMOVQ2M K1, ZMM0;;VXORPS ZMM0, ZMM0, ZMM0
Chain latency: 3

Code:

   0:	62 f1 f5 49 d4 c2    	vpaddq zmm0{k1},zmm1,zmm2
   6:	62 f2 fe 48 39 c8    	vpmovq2m k1,zmm0
   c:	62 f1 7c 48 57 c0    	vxorps zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.0
- Reference cycles: 2.61
- UOPS_EXECUTED.THREAD: 2.0

Experiment 3

Instruction: VPADDQ ZMM0 {K1}, ZMM1, ZMM2
Chain instruction: VPTESTNMQ K1 {K1}, ZMM0, ZMM0
Chain latency: 3

Code:

   0:	62 f1 f5 49 d4 c2    	vpaddq zmm0{k1},zmm1,zmm2
   6:	62 f2 fe 49 27 c8    	vptestnmq k1{k1},zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.0
- Reference cycles: 3.07
- UOPS_EXECUTED.THREAD: 2.0

Experiment 4 (with dependency-breaking instructions)

Instruction: VPADDQ ZMM0 {K1}, ZMM1, ZMM2
Chain instructions: VPTESTNMQ K1 {K1}, ZMM0, ZMM0;;VXORPS ZMM0, ZMM0, ZMM0
Chain latency: 3

Code:

   0:	62 f1 f5 49 d4 c2    	vpaddq zmm0{k1},zmm1,zmm2
   6:	62 f2 fe 49 27 c8    	vptestnmq k1{k1},zmm0,zmm0
   c:	62 f1 7c 48 57 c0    	vxorps zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.0
- Reference cycles: 2.91
- UOPS_EXECUTED.THREAD: 2.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VPADDQ ZMM0 {K1}, ZMM1, ZMM2
Chain instruction: VPMOVQ2M K1, ZMM0
Chain latency: 3

Code:

   0:	62 f1 f5 49 d4 c2    	vpaddq zmm0{k1},zmm1,zmm2
   6:	62 f2 fe 48 39 c8    	vpmovq2m k1,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VPADDQ ZMM0  {K1}, ZMM1, ZMM2;
VPADDQ ZMM1  {K1}, ZMM0, ZMM2;
VPADDQ ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.0
- Reference cycles: 2.91
- UOPS_EXECUTED.THREAD: 2.0

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPADDQ ZMM0 {K1}, ZMM1, ZMM2
Chain instructions: VPMOVQ2M K1, ZMM0;;VXORPS ZMM0, ZMM0, ZMM0
Chain latency: 3

Code:

   0:	62 f1 f5 49 d4 c2    	vpaddq zmm0{k1},zmm1,zmm2
   6:	62 f2 fe 48 39 c8    	vpmovq2m k1,zmm0
   c:	62 f1 7c 48 57 c0    	vxorps zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VPADDQ ZMM0  {K1}, ZMM1, ZMM2;
VPADDQ ZMM1  {K1}, ZMM0, ZMM2;
VPADDQ ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.0
- Reference cycles: 2.45
- UOPS_EXECUTED.THREAD: 2.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VPADDQ ZMM0 {K1}, ZMM1, ZMM2
Chain instruction: VPTESTNMQ K1 {K1}, ZMM0, ZMM0
Chain latency: 3

Code:

   0:	62 f1 f5 49 d4 c2    	vpaddq zmm0{k1},zmm1,zmm2
   6:	62 f2 fe 49 27 c8    	vptestnmq k1{k1},zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VPADDQ ZMM0  {K1}, ZMM1, ZMM2;
VPADDQ ZMM1  {K1}, ZMM0, ZMM2;
VPADDQ ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.0
- Reference cycles: 3.07
- UOPS_EXECUTED.THREAD: 2.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPADDQ ZMM0 {K1}, ZMM1, ZMM2
Chain instructions: VPTESTNMQ K1 {K1}, ZMM0, ZMM0;;VXORPS ZMM0, ZMM0, ZMM0
Chain latency: 3

Code:

   0:	62 f1 f5 49 d4 c2    	vpaddq zmm0{k1},zmm1,zmm2
   6:	62 f2 fe 49 27 c8    	vptestnmq k1{k1},zmm0,zmm0
   c:	62 f1 7c 48 57 c0    	vxorps zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VPADDQ ZMM0  {K1}, ZMM1, ZMM2;
VPADDQ ZMM1  {K1}, ZMM0, ZMM2;
VPADDQ ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.0
- Reference cycles: 2.76
- UOPS_EXECUTED.THREAD: 2.0

Latency operand 3 → 1: 1

Experiment 1

Instruction: VPADDQ ZMM1 {K1}, ZMM0, ZMM2
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0
Chain latency: 5

Code:

   0:	62 f1 fd 49 d4 ca    	vpaddq zmm1{k1},zmm0,zmm2
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.29
- UOPS_EXECUTED.THREAD: 6.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VPADDQ ZMM1 {K1}, ZMM0, ZMM2
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;;VXORPS ZMM1, ZMM1, ZMM1
Chain latency: 5

Code:

   0:	62 f1 fd 49 d4 ca    	vpaddq zmm1{k1},zmm0,zmm2
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  29:	62 f1 74 48 57 c9    	vxorps zmm1,zmm1,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 6.0
- Reference cycles: 4.6
- UOPS_EXECUTED.THREAD: 6.0

Experiment 3

Instruction: VPADDQ ZMM1 {K1}, ZMM0, ZMM2
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0
Chain latency: 5

Code:

   0:	62 f1 fd 49 d4 ca    	vpaddq zmm1{k1},zmm0,zmm2
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.45
- UOPS_EXECUTED.THREAD: 6.0

Experiment 4 (with dependency-breaking instructions)

Instruction: VPADDQ ZMM1 {K1}, ZMM0, ZMM2
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;;VXORPS ZMM1, ZMM1, ZMM1
Chain latency: 5

Code:

   0:	62 f1 fd 49 d4 ca    	vpaddq zmm1{k1},zmm0,zmm2
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  24:	62 f1 74 48 57 c9    	vxorps zmm1,zmm1,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM2, ZMM2, ZMM2

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 6.0
- Reference cycles: 4.45
- UOPS_EXECUTED.THREAD: 6.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VPADDQ ZMM1 {K1}, ZMM0, ZMM2
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0
Chain latency: 5

Code:

   0:	62 f1 fd 49 d4 ca    	vpaddq zmm1{k1},zmm0,zmm2
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM2, ZMM2, ZMM2;
VPADDQ ZMM1  {K1}, ZMM0, ZMM2;
VPADDQ ZMM0  {K1}, ZMM1, ZMM2;
VPADDQ ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.45
- UOPS_EXECUTED.THREAD: 6.0

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPADDQ ZMM1 {K1}, ZMM0, ZMM2
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;;VXORPS ZMM1, ZMM1, ZMM1
Chain latency: 5

Code:

   0:	62 f1 fd 49 d4 ca    	vpaddq zmm1{k1},zmm0,zmm2
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  29:	62 f1 74 48 57 c9    	vxorps zmm1,zmm1,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM2, ZMM2, ZMM2;
VPADDQ ZMM1  {K1}, ZMM0, ZMM2;
VPADDQ ZMM0  {K1}, ZMM1, ZMM2;
VPADDQ ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 6.0
- Reference cycles: 4.29
- UOPS_EXECUTED.THREAD: 6.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VPADDQ ZMM1 {K1}, ZMM0, ZMM2
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0
Chain latency: 5

Code:

   0:	62 f1 fd 49 d4 ca    	vpaddq zmm1{k1},zmm0,zmm2
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM2, ZMM2, ZMM2;
VPADDQ ZMM1  {K1}, ZMM0, ZMM2;
VPADDQ ZMM0  {K1}, ZMM1, ZMM2;
VPADDQ ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 3.99
- UOPS_EXECUTED.THREAD: 6.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPADDQ ZMM1 {K1}, ZMM0, ZMM2
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;;VXORPS ZMM1, ZMM1, ZMM1
Chain latency: 5

Code:

   0:	62 f1 fd 49 d4 ca    	vpaddq zmm1{k1},zmm0,zmm2
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  24:	62 f1 74 48 57 c9    	vxorps zmm1,zmm1,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM0, ZMM0, ZMM0;
VXORPS ZMM2, ZMM2, ZMM2;
VPADDQ ZMM1  {K1}, ZMM0, ZMM2;
VPADDQ ZMM0  {K1}, ZMM1, ZMM2;
VPADDQ ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 6.0
- Reference cycles: 4.14
- UOPS_EXECUTED.THREAD: 6.0

Latency operand 4 → 1: 1

Experiment 1

Instruction: VPADDQ ZMM1 {K1}, ZMM2, ZMM0
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0
Chain latency: 5

Code:

   0:	62 f1 ed 49 d4 c8    	vpaddq zmm1{k1},zmm2,zmm0
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.29
- UOPS_EXECUTED.THREAD: 6.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VPADDQ ZMM1 {K1}, ZMM2, ZMM0
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;;VXORPS ZMM1, ZMM1, ZMM1
Chain latency: 5

Code:

   0:	62 f1 ed 49 d4 c8    	vpaddq zmm1{k1},zmm2,zmm0
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  29:	62 f1 74 48 57 c9    	vxorps zmm1,zmm1,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 6.0
- Reference cycles: 4.14
- UOPS_EXECUTED.THREAD: 6.0

Experiment 3

Instruction: VPADDQ ZMM1 {K1}, ZMM2, ZMM0
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0
Chain latency: 5

Code:

   0:	62 f1 ed 49 d4 c8    	vpaddq zmm1{k1},zmm2,zmm0
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 3.99
- UOPS_EXECUTED.THREAD: 6.0

Experiment 4 (with dependency-breaking instructions)

Instruction: VPADDQ ZMM1 {K1}, ZMM2, ZMM0
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;;VXORPS ZMM1, ZMM1, ZMM1
Chain latency: 5

Code:

   0:	62 f1 ed 49 d4 c8    	vpaddq zmm1{k1},zmm2,zmm0
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  24:	62 f1 74 48 57 c9    	vxorps zmm1,zmm1,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM0, ZMM0, ZMM0

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 6.0
- Reference cycles: 3.99
- UOPS_EXECUTED.THREAD: 6.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VPADDQ ZMM1 {K1}, ZMM2, ZMM0
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0
Chain latency: 5

Code:

   0:	62 f1 ed 49 d4 c8    	vpaddq zmm1{k1},zmm2,zmm0
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM0, ZMM0, ZMM0;
VPADDQ ZMM1  {K1}, ZMM0, ZMM2;
VPADDQ ZMM2  {K1}, ZMM0, ZMM1;
VPADDQ ZMM0  {K1}, ZMM1, ZMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.14
- UOPS_EXECUTED.THREAD: 6.0

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPADDQ ZMM1 {K1}, ZMM2, ZMM0
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;;VXORPS ZMM1, ZMM1, ZMM1
Chain latency: 5

Code:

   0:	62 f1 ed 49 d4 c8    	vpaddq zmm1{k1},zmm2,zmm0
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  29:	62 f1 74 48 57 c9    	vxorps zmm1,zmm1,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM0, ZMM0, ZMM0;
VPADDQ ZMM1  {K1}, ZMM0, ZMM2;
VPADDQ ZMM2  {K1}, ZMM0, ZMM1;
VPADDQ ZMM0  {K1}, ZMM1, ZMM2

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 6.0
- Reference cycles: 4.14
- UOPS_EXECUTED.THREAD: 6.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VPADDQ ZMM1 {K1}, ZMM2, ZMM0
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0
Chain latency: 5

Code:

   0:	62 f1 ed 49 d4 c8    	vpaddq zmm1{k1},zmm2,zmm0
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM0, ZMM0, ZMM0;
VPADDQ ZMM1  {K1}, ZMM0, ZMM2;
VPADDQ ZMM2  {K1}, ZMM0, ZMM1;
VPADDQ ZMM0  {K1}, ZMM1, ZMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.0
- Reference cycles: 4.6
- UOPS_EXECUTED.THREAD: 6.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VPADDQ ZMM1 {K1}, ZMM2, ZMM0
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;;VXORPS ZMM1, ZMM1, ZMM1
Chain latency: 5

Code:

   0:	62 f1 ed 49 d4 c8    	vpaddq zmm1{k1},zmm2,zmm0
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  24:	62 f1 74 48 57 c9    	vxorps zmm1,zmm1,zmm1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS ZMM1, ZMM1, ZMM1;
VXORPS ZMM2, ZMM2, ZMM2;
VXORPS ZMM0, ZMM0, ZMM0;
VPADDQ ZMM1  {K1}, ZMM0, ZMM2;
VPADDQ ZMM2  {K1}, ZMM0, ZMM1;
VPADDQ ZMM0  {K1}, ZMM1, ZMM2

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 6.0
- Reference cycles: 3.83
- UOPS_EXECUTED.THREAD: 6.0

VPADDQ (ZMM, K, ZMM, ZMM) - Latency

Operands

Latency operand 1 → 1: 1

Latency operand 2 → 1: 1

Latency operand 3 → 1: 1

Latency operand 4 → 1: 1

Latency operand 1 → 1: 1

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1: 1

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Latency operand 3 → 1: 1

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Latency operand 4 → 1: 1

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)