VGATHERDPD (ZMM, K, VSIB_YMM) - Latency


Operands


Latency operand 1 → 1: 1

Latency operand 1 → 2: 4

Latency operand 2 → 1: 21

Latency operand 2 → 2: 2

Latency operand 3 → 1 (address, base register): ≤18

Latency operand 3 → 1 (address, index register): ≤21

Latency operand 3 → 1 (memory): ≤13


Latency operand 1 → 1: 1

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)


Latency operand 1 → 2: 4

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 1: 21

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 2: 2

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)


Latency operand 3 → 1 (address, base register): ≤18

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 3 → 1 (address, index register): ≤21

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 3 → 1 (memory): ≤13

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)